公开(公告)号：US20250088340A1

公开(公告)日：2025-03-13

申请号：US18464512

申请日：2023-09-11

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  Lewis F. LAHR ,  William HOOPER ,  Matthew PUZEY

IPC: H04L5/14 ,  H04L7/00

Abstract: A communication system includes a plurality of nodes connected in a daisy-chain via respective bus links, wherein the plurality of nodes are configured for full duplex, synchronized communication via a carrier-based modulation scheme over the bus links. A node is configured to: transmit a downstream synchronization control header (DnSCH) to a downstream node; receive an upstream synchronization response header (UpSRH) from the downstream node; measure a delay between the DnSCH and the UpSRH; send delay information to the downstream node in a DnSCH; receive a time adjusted UpSRH; and communicate with the downstream node and any upstream node over frames based on the delay information. The frames may include a header; a flexible payload defined by a stream mapping that assigns a byte location within the flexible payload to a stream; and a footer.

公开(公告)号：US20170220502A1

公开(公告)日：2017-08-03

申请号：US15411846

申请日：2017-01-20

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  William HOOPER ,  Lewis F. LAHR

IPC: G06F13/364 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/404 ,  G06F13/4282

Abstract: Disclosed herein are systems and techniques for general purpose input/output (GPIO)-to-GPIO communication in a multi-node, daisy-chained network. In some embodiments, a transceiver may support GPIO between multiple nodes, without host intervention after initial programming. In some such embodiments, the host may be required only for initial setup of the virtual ports. In some embodiments, GPIO pins can be inputs (which may change virtual ports) or outputs (which may reflect virtual ports). In some embodiments, multiple virtual ports may be mapped to one GPIO output pin (with the values OR'ed together, for example). In some embodiments, multiple GPIO input pins may be mapped to one virtual port. For example, multiple GPIO input pin values may be OR'ed together, even if they come from multiple nodes.

公开(公告)号：US20220156219A1

公开(公告)日：2022-05-19

申请号：US17589715

申请日：2022-01-31

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  Miguel A. CHAVEZ ,  Lewis F. LAHR ,  William HOOPER ,  Robert Adams ,  Peter SEALEY

IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

公开(公告)号：US20210157766A1

公开(公告)日：2021-05-27

申请号：US17110126

申请日：2020-12-02

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  Lewis F. LAHR ,  William HOOPER

IPC: G06F13/42

Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

公开(公告)号：US20200257646A1

公开(公告)日：2020-08-13

申请号：US16859611

申请日：2020-04-27

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  Miguel A. CHAVEZ ,  Lewis F. LAHR ,  William HOOPER ,  Robert Adams ,  Peter SEALEY

IPC: G06F13/42 ,  G06F13/364 ,  H04L12/403 ,  H04B3/54 ,  G06F1/26 ,  G05B19/042 ,  G05B19/418

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

公开(公告)号：US20190278733A1

公开(公告)日：2019-09-12

申请号：US16427131

申请日：2019-05-30

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  Miguel CHAVEZ ,  Lewis F. LAHR ,  William HOOPER ,  Robert Adams ,  Peter SEALEY

IPC: G06F13/42 ,  G06F13/364 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.