公开(公告)号：US10551215B2

公开(公告)日：2020-02-04

申请号：US14737403

申请日：2015-06-11

Applicant: ANALOG DEVICES GLOBAL UNLIMITED COMPANY

Inventor： Eoin E. English ,  Javier Calpe Maravilla ,  Robert Guyol ,  Alan J. O'Donnell ,  Maria Jose Martinez ,  Jan Kubik ,  Krystian Balicki

IPC: G01D5/20

Abstract: An embodiment of a position sensing system includes a signal generation circuit to generate an excitation signal according to a selected characteristic signal, a drive circuit to drive an excitation source with the excitation signal, an input circuit to receive a sensor output while driving the excitation source, a signal detection circuit to identify a component of the sensor output corresponding to the characteristic signal, and a control circuit to determine the position of the movable object as a function of the identified component of the sensor output. The positioning system may be included an electronic camera, where the movable object may be a lens. The excitation source may be a conductive coil, the excitation a magnetic field, and the sensor a magneto resistive sensor. Alternatively, the excitation source may be an optical excitation source, the excitation an optical excitation, and the sensor an optical sensor.

公开(公告)号：US20190148229A1

公开(公告)日：2019-05-16

申请号：US15810836

申请日：2017-11-13

Applicant: Analog Devices Global Unlimited Company

Inventor： Jan Kubik ,  Bernard P. Stenson ,  Michael Noel Morrissey

IPC: H01L21/768 ,  H01L49/02 ,  H01L21/288 ,  H01L21/033 ,  H01L23/522

Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

公开(公告)号：US20180358166A1

公开(公告)日：2018-12-13

申请号：US16003621

申请日：2018-06-08

Applicant: Analog Devices Global Unlimited Company

Inventor： Jan Kubik ,  Bernard Patrick Stenson ,  Michael Morrissey

IPC: H01F27/26 ,  H01F27/28

CPC classification number: H01F27/263 ,  H01F27/2804 ,  H01F2027/2809 ,  H01F2027/2819

Abstract: Techniques for fabricating low-loss magnetic vias within a magnetic core are provided. According to some embodiments, vias with small, well-defined sizes may be fabricated without reliance on precise alignment of layers. According to some embodiments, a magnetic core including a low-loss magnetic via can be wrapped around conductive coils of an inductor. The low-loss magnetic vias can improve performance of an inductive component by improving the quality factor relative to higher loss magnetic vias.

公开(公告)号：US20200328114A1

公开(公告)日：2020-10-15

申请号：US16914900

申请日：2020-06-29

Applicant: Analog Devices Global Unlimited Company

Inventor： Jan Kubik ,  Bernard P. Stenson ,  Michael Noel Morrissey

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/522 ,  H01L21/288 ,  H01L21/033 ,  C23C18/16 ,  H01L23/532 ,  C25D5/02 ,  C25D7/12 ,  C25D5/10 ,  H05K3/24 ,  H05K3/18 ,  H05K3/42

Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

公开(公告)号：US10699948B2

公开(公告)日：2020-06-30

申请号：US15810836

申请日：2017-11-13

Applicant: Analog Devices Global Unlimited Company

Inventor： Jan Kubik ,  Bernard P. Stenson ,  Michael Noel Morrissey

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/288 ,  H01L21/033 ,  C23C18/16 ,  H01L23/532 ,  H01L49/02 ,  C25D5/02 ,  C25D7/12 ,  C25D5/10 ,  H05K3/24 ,  H05K3/18 ,  H05K3/42 ,  H05K1/02

Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.