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公开(公告)号：US07492648B2
公开(公告)日：2009-02-17
申请号：US11387879
申请日：2006-03-24
CPC分类号： G11C8/12 , G11C7/02 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.
摘要翻译： 一种用于减少包括多个存储体的半导体存储器件中的缺陷漏电流的方法，每个存储体包括多个存储器阵列和包括多个读出放大器的读出放大器列，其中存在位于并共享的读出放大器列 由存储器阵列的对立面。 根据存储体中的异常位线泄漏的存在和位置，独立地为多个存储体中的每一个存储至少一个存储体特定的隔离控制信号。 所述至少一个存储体特定的隔离控制信号被提供给相应的存储体中的至少一个读出放大器列，以将至少一个侧面隔离到相应的存储体中处于未选择状态的至少一个存储器阵列。
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公开(公告)号：US20070223302A1
公开(公告)日：2007-09-27
申请号：US11387879
申请日：2006-03-24
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/02 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.
摘要翻译： 一种用于减少包括多个存储体的半导体存储器件中的缺陷漏电流的方法，每个存储体包括多个存储器阵列和包括多个读出放大器的读出放大器列，其中存在位于并共享的读出放大器列 由存储器阵列的对立面。 根据存储体中的异常位线泄漏的存在和位置，独立地为多个存储体中的每一个存储至少一个存储体特定的隔离控制信号。 所述至少一个存储体特定的隔离控制信号被提供给相应的存储体中的至少一个读出放大器列，以将至少一个侧面隔离到相应的存储体中处于未选择状态的至少一个存储器阵列。
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3.发明申请公开(公告)号：US20070223296A1
公开(公告)日：2007-09-27
申请号：US11387882
申请日：2006-03-24
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C7/12 , G11C2207/005
摘要： A semiconductor memory device and method are provided in which leakage current of the memory device is reduced. A sense amplifier is isolated from a memory array that has an anomalous bitline leakage when the memory array is not selected.
摘要翻译： 提供一种半导体存储器件和方法，其中存储器件的漏电流减小。 当未选择存储器阵列时，读出放大器与存储器阵列隔离，该阵列具有异常的位线泄漏。
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4.发明申请Separate sense amplifier precharge node in a semiconductor memory device 审中-公开在半导体存储器件中分离读出放大器预充电节点公开(公告)号：US20070247938A1
公开(公告)日：2007-10-25
申请号：US11410255
申请日：2006-04-25
申请人： Christopher Miller , Andre Sturm
发明人： Christopher Miller , Andre Sturm
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C7/02 , G11C7/065 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/005
摘要： A method and memory device are provided in which sense nodes of a sense amplifier in a semiconductor memory device are internally precharged independent of equalize and precharge operations on bitlines of a memory array associated with the sense amplifier.
摘要翻译： 提供了一种方法和存储器件，其中半导体存储器件中的读出放大器的感测节点在内部预充电，独立于与读出放大器相关联的存储器阵列的位线上的均衡和预充电操作。
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公开(公告)号：US07840876B2
公开(公告)日：2010-11-23
申请号：US11676774
申请日：2007-02-20
申请人： Andre Sturm , Harald Streif
发明人： Andre Sturm , Harald Streif
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1052 , G11C8/08 , G11C8/12 , G11C8/14 , G11C11/4096
摘要： The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled.
摘要翻译： 本发明包括具有数据存储器和纠错码控制电路的存储器件。 数据存储器存储用于纠错的数据奇偶校验信息。 纠错码控制电路被配置为接收指示是否使用纠错模式的选择信号。 当启用纠错模式时，禁用访问存储奇偶校验信息的存储部分的电源。
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公开(公告)号：US20080201626A1
公开(公告)日：2008-08-21
申请号：US11676774
申请日：2007-02-20
申请人： Andre Sturm , Harald Streif
发明人： Andre Sturm , Harald Streif
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1052 , G11C8/08 , G11C8/12 , G11C8/14 , G11C11/4096
摘要： The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled.
摘要翻译： 本发明包括具有数据存储器和纠错码控制电路的存储器件。 数据存储器存储用于纠错的数据奇偶校验信息。 纠错码控制电路被配置为接收指示是否使用纠错模式的选择信号。 当启用纠错模式时，禁用访问存储奇偶校验信息的存储部分的电源。
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7.发明申请公开(公告)号：US20080238468A1
公开(公告)日：2008-10-02
申请号：US11727291
申请日：2007-03-26
申请人： Andre Sturm , Thomas Vogelsang , Marc Walter
发明人： Andre Sturm , Thomas Vogelsang , Marc Walter
IPC分类号： G01R31/02
CPC分类号： G11C29/46
摘要： In a method or apparatus such as an integrated circuit (IC) chip including a plurality of circuits for executing a plurality of testmodes, a testmode entry code specifying one of the plurality of testmodes and one of an unrestricted private testmode category and a restricted public testmode category is received. Execution of only a public testmode of the plurality of testmodes is enabled when the testmode entry code specifies the restricted public testmode category. Execution of all of the plurality of testmodes is enabled when the testmode entry code specifies the unrestricted private testmode category.
摘要翻译： 在包括用于执行多个测试模式的多个电路的集成电路（IC）芯片的方法或装置中，指定多个测试模式之一的测试模式条目代码以及无限制的私有测试模式类别和受限的公共测试模式之一 类别被收到。 当测试模式条目代码指定受限制的公共测试模式类别时，仅启用多个测试模式的公共测试模式。 当测试模式条目代码指定不受限制的私有测试模式类别时，启用所有多个测试模式的所有操作。
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8.发明申请Active write current adjustment for magneto-resistive random access memory 审中-公开用于磁阻随机存取存储器的有效写入电流调整公开(公告)号：US20080080232A1
公开(公告)日：2008-04-03
申请号：US11529569
申请日：2006-09-28
CPC分类号： G11C11/16
摘要： In a method of programming a magneto resistive memory cell, a first magnetic field is applied to the magneto resistive memory cell. It is determined whether the magneto resistive memory cell meets a programming criterion. In case that the magneto resistive memory cell does not meet the programming criterion, a second magnetic field, which is higher or lower than the first magnetic field, is applied to the magneto resistive memory cell. It is then determined whether the magneto resistive memory cell meets a programming criterion. The magnetic field is increased or decreased in case that the magneto resistive memory cell does not meet the programming criterion until the magneto resistive memory cell meets the programming criterion.
摘要翻译： 在编写磁阻存储器单元的方法中，第一磁场被施加到磁阻存储器单元。 确定磁阻存储器单元是否满足编程标准。 在磁阻存储器单元不满足编程标准的情况下，将高于或低于第一磁场的第二磁场施加到磁阻存储器单元。 然后确定磁阻存储器单元是否满足编程标准。 在磁阻存储器单元不满足编程标准直到磁阻存储器单元满足编程标准的情况下，磁场增加或减小。
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