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    High-voltage high-speed SOI MOSFET
    1.
    发明授权
    High-voltage high-speed SOI MOSFET 有权
    高压高速SOI MOSFET

    公开(公告)号：US06512269B1

    公开(公告)日：2003-01-28

    申请号：US09657315

    申请日：2000-09-07

    申请人： Andres Bryant ,  Edward Joseph Nowak ,  Minh Ho Tong

    发明人： Andres Bryant ,  Edward Joseph Nowak ,  Minh Ho Tong

    IPC分类号： H01L2701

    CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384

    摘要： A semiconductor device including an SOI substrate; a plurality of diffusion regions in substrate, separated by, and abutting a plurality of body regions in said substrate, a first one of the body regions and its abutting diffusion regions having a first width and successive ones of the body regions and their abutting diffusion regions having successively smaller widths; and a plurality of gates each over one of the plurality of body regions and separated from the body regions by a dielectric material, said plurality of gates connected to a common voltage terminal.

    摘要翻译： 一种包括SOI衬底的半导体器件; 衬底中的多个扩散区域，分隔并邻接所述衬底中的多个主体区域，身体区域中的第一个和其邻接扩散区域具有第一宽度和连续的身体区域及其邻接扩散区域 具有相继较小的宽度; 以及多个栅极，每个栅极分别位于多个主体区域中的一个上，并且通过电介质材料与主体区域分离，所述多个栅极连接到公共电压端子。

    Domino logic circuit having multiplicity of gate dielectric thicknesses
    2.
    发明授权
    Domino logic circuit having multiplicity of gate dielectric thicknesses 有权
    具有多个栅介质厚度的多米诺逻辑电路

    公开(公告)号：US06404236B1

    公开(公告)日：2002-06-11

    申请号：US09811967

    申请日：2001-03-19

    申请人： Kerry Bernstein ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Edward Joseph Nowak ,  Minh Ho Tong

    发明人： Kerry Bernstein ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Edward Joseph Nowak ,  Minh Ho Tong

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. Connected to a power supply, the precharge transistor receives a clock input. The isolation transistor is connected to ground and also receives the clock input. Each of the input transistors, which are coupled between the precharge transistor and the isolation transistor, receives a signal input. The gate dielectric thickness of the evaluate transistors is less than the gate dielectric thickness of the precharge transistor.

    摘要翻译： 公开了具有时钟预充电的多米诺骨牌逻辑电路。 多米诺骨牌逻辑电路包括预充电晶体管，隔离晶体管和多个评估晶体管。 连接到电源，预充电晶体管接收时钟输入。 隔离晶体管连接到地，并接收时钟输入。 耦合在预充电晶体管和隔离晶体管之间的每个输入晶体管接收信号输入。 评估晶体管的栅介质厚度小于预充电晶体管的栅介质厚度。

    Method of forming semiconductor device with decoupling capacitance
    3.
    发明授权
    Method of forming semiconductor device with decoupling capacitance 失效
    用去耦电容形成半导体器件的方法

    公开(公告)号：US06365484B1

    公开(公告)日：2002-04-02

    申请号：US09634970

    申请日：2000-08-09

    申请人： Edward Joseph Nowak ,  Minh Ho Tong

    发明人： Edward Joseph Nowak ,  Minh Ho Tong

    IPC分类号： H01L2120

    CPC分类号： H01L27/1203 ,  H01L27/0248 ,  H01L27/088

    摘要： A semiconductor device is disclosed that provides a decoupling capacitance and method for the same. The semiconductor device includes a first circuit region having a first device layer over an isolation layer and a second circuit region adjacent the first circuit region having a second device layer over a well. An implant layer is implanted beneath the isolation layer in the first circuit region, which will connect to the well of the second circuit region.

    摘要翻译： 公开了提供一种去耦电容的半导体器件及其方法。 半导体器件包括具有在隔离层上的第一器件层的第一电路区域和与第一电路区域相邻的第二电路区域，该第二电路区域在阱上具有第二器件层。 在第一电路区域中的隔离层下方植入注入层，其将连接到第二电路区域的阱。

    Voltage translation circuit for mixed voltage applications
    5.
    发明授权
    Voltage translation circuit for mixed voltage applications 失效
    电压转换电路用于混合电压应用

    公开(公告)号：US5973508A

    公开(公告)日：1999-10-26

    申请号：US859934

    申请日：1997-05-21

    申请人： Edward Joseph Nowak ,  Minh Ho Tong

    发明人： Edward Joseph Nowak ,  Minh Ho Tong

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018521

    摘要： A voltage translation circuit for translating signals from a first voltage range to a second voltage range is disclosed. The voltage translation circuit includes a first inverter having an input that receives an intermediate signal and an output that provides an output signal having voltage levels that are latched to high and low states of the second voltage range. A second inverter is provided having an input connected to the first inverter output and an output connected to the first inverter input. A capacitor is also provided having an input that receives an input signal of the first voltage range and an output that provides the intermediate signal of the second voltage range. In addition, a pair of diodes are connected in series between a pair of voltage sources that provides high and low states of the second voltage range. The interconnected terminals of the pair of diodes are connected to the output of the capacitor.

    摘要翻译： 公开了一种用于将信号从第一电压范围转换到第二电压范围的电压转换电路。 电压转换电路包括具有接收中间信号的输入的第一反相器和提供具有被锁存到第二电压范围的高和低状态的电压电平的输出信号的输出。 提供了具有连接到第一反相器输出的输入和连接到第一反相器输入的输出的第二反相器。 还提供了具有接收第一电压范围的输入信号的输入端和提供第二电压范围的中间信号的输出的电容器。 此外，一对二极管串联连接在提供第二电压范围的高和低状态的一对电压源之间。 一对二极管的互连端子连接到电容器的输出端。

    Dynamic threshold voltage devices with low gate to substrate resistance
    6.
    发明授权
    Dynamic threshold voltage devices with low gate to substrate resistance 有权
    动态门限电压器件具有低栅极到衬底电阻

    公开(公告)号：US06459106B2

    公开(公告)日：2002-10-01

    申请号：US09753521

    申请日：2001-01-03

    申请人： Andres A. Bryant ,  Edward Joseph Nowak ,  Minh Ho Tong

    发明人： Andres A. Bryant ,  Edward Joseph Nowak ,  Minh Ho Tong

    IPC分类号： H01L29768

    CPC分类号： H01L21/84 ,  H01L29/78609 ,  H01L29/78612

    摘要： Described is a dynamic threshold field effect transistor (DTFET) that includes a gate-to-body contact structure within the gate. By forming the gate-to-body contact structure that can reduce the gate-to-body contact resistance and increase the device packing density, the DTFET can be used in silicon on insulator (SOI) technologies and take full advantages of the DT-CMOS performance benefit.

    摘要翻译： 描述了一种动态阈值场效应晶体管（DTFET），其包括栅极内的栅对体接触结构。 通过形成能够降低栅对体接触电阻并增加器件封装密度的栅对体接触结构，DTFET可用于绝缘体上硅（SOI）技术，并充分利用了DT-CMOS 性能优势。

    Semiconductor device with decoupling capacitance
    7.
    发明授权
    Semiconductor device with decoupling capacitance 失效
    具有去耦电容的半导体器件

    公开(公告)号：US06191451B1

    公开(公告)日：2001-02-20

    申请号：US09016026

    申请日：1998-01-30

    申请人： Edward Joseph Nowak ,  Minh Ho Tong

    发明人： Edward Joseph Nowak ,  Minh Ho Tong

    IPC分类号： H01L2701

    CPC分类号： H01L27/1203 ,  H01L27/0248 ,  H01L27/088

    摘要： A semiconductor device is disclosed that provides a decoupling capacitance and method for the same. The semiconductor device includes a first circuit region having a first device layer over an isolation layer and a second circuit region adjacent the first circuit region having a second device layer over a well. An implant layer is implanted beneath the isolation layer in the first circuit region, which will connect to the well of the second circuit region.

    摘要翻译： 公开了提供一种去耦电容的半导体器件及其方法。 半导体器件包括具有在隔离层上的第一器件层的第一电路区域和与第一电路区域相邻的第二电路区域，该第二电路区域在阱上具有第二器件层。 在第一电路区域中的隔离层下方植入注入层，其将连接到第二电路区域的阱。

    Antifuse circuit using standard MOSFET devices
    8.
    发明授权
    Antifuse circuit using standard MOSFET devices 失效
    防漏电路采用标准MOSFET器件

    公开(公告)号：US5672994A

    公开(公告)日：1997-09-30

    申请号：US576026

    申请日：1995-12-21

    申请人： Wai-Ming William Au ,  Edward Joseph Nowak ,  Minh Ho Tong

    发明人： Wai-Ming William Au ,  Edward Joseph Nowak ,  Minh Ho Tong

    IPC分类号： G11C17/16 ,  H01L23/525 ,  H01H37/76

    CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L2924/0002

    摘要： A programmable device is formed from a field-effect transistor. Specifically, the present invention generally related to integrated circuit (IC) structures and more particularly, to an improved antifuse structure for use in programming redundant and customizable IC chips. The anti-fuse is NFET made of MOS material and formed at a face of a semiconductor layer having an n-type doped source, and drain region, and a p-type doped channel region separating the source and drain regions. The device is programmed by applying a high voltage to the NFET drain to form a hot spot located along the channel width of the drain and thereby forming a bridge, which now has less resistance than the surrounding channel material, to the NFET source.

    摘要翻译： 可编程器件由场效应晶体管形成。 具体地，本发明一般涉及集成电路（IC）结构，更具体地说，涉及用于编程冗余且可定制的IC芯片的改进的反熔丝结构。 反熔丝是由MOS材料制成的NFET，并且形成在具有n型掺杂源的半导体层的表面和漏极区域以及分离源极和漏极区域的p型掺杂沟道区域。 通过向NFET漏极施加高电压来形成器件，以形成沿着漏极的沟道宽度定位的热点，从而形成现在具有比周围通道材料更小的电阻到NFET源的桥。

    Leak tolerant low power dynamic circuits
    10.
    发明授权
    Leak tolerant low power dynamic circuits 失效
    耐漏电低功率动态电路

    公开(公告)号：US5831452A

    公开(公告)日：1998-11-03

    申请号：US803582

    申请日：1997-02-20

    申请人： Edward Joseph Nowak ,  Minh Ho Tong ,  Lawrence G. Heller

    发明人： Edward Joseph Nowak ,  Minh Ho Tong ,  Lawrence G. Heller

    IPC分类号： H03K19/096 ,  H03K19/0948

    CPC分类号： H03K19/0963

    摘要： A novel precharge circuit is provided for dynamic CMOS logic circuits which are immune to leakage currents and reduce overall power consumption. The circuit comprises a precharge transistor for precharging a node to a high voltage level indicting a first logic state during a standby mode. Thereafter, during an active mode, the node may or may not be discharged by connected logic circuitry. If the node is discharged, then an additional transistor is provided to inhibit the precharging of the already charged node during a subsequent standby mode. Similarly, if the node is not discharged, a small keeper transistor is provided to keep the node at a fully precharged level.

    摘要翻译： 为动态CMOS逻辑电路提供了一种新颖的预充电电路，其免于漏电流并降低总体功耗。 电路包括用于在待机模式期间将节点预充电到指示第一逻辑状态的高电压电平的预充电晶体管。 此后，在活动模式期间，节点可以被连接的逻辑电路放电，也可以不被放电。 如果节点放电，则提供附加晶体管以在随后的待机模式期间禁止已经充电的节点的预充电。 类似地，如果节点不被放电，则提供小的保持晶体管以保持节点处于完全预充电电平。