公开(公告)号：US07149862B2

公开(公告)日：2006-12-12

申请号：US10933478

申请日：2004-09-03

申请人： Andrew David Tune ,  Peter James Aldworth ,  Simon Charles Watt ,  Lionel Belnet ,  David Hennah Mansell

发明人： Andrew David Tune ,  Peter James Aldworth ,  Simon Charles Watt ,  Lionel Belnet ,  David Hennah Mansell

IPC分类号： G06F12/00

CPC分类号： G06F12/1441

摘要： A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request. Further, access control logic is provided which is associated with the slave device, the access control logic being operable to receive the access request from the bus and an indication of the partition from the control storage and, if the access request is a non-secure access request, to prevent access to the secure region.

摘要翻译： 提供了一种用于控制对从设备的访问的数据处理设备和方法，该从设备具有与之相关联的地址范围。 该装置包括可编程的控制存储器，用于定义识别地址范围中的安全区域和非安全区域的分区，数据处理设备支持包括安全模式的多种操作模式，并且控制存储器仅可由 软件在安全模式下执行。 主设备被布置为在总线上发出访问请求，该访问请求标识地址范围内的一系列地址，并且包括指示该访问请求是安全访问请求还是非安全访问请求的控制信号。 安全区域只能通过安全访问请求访问。 此外，提供与从设备相关联的访问控制逻辑，访问控制逻辑可操作以从总线接收访问请求以及来自控制存储器的分区的指示，以及如果访问请求是非安全的 访问请求，以防止访问安全区域。

公开(公告)号：US20090319718A1

公开(公告)日：2009-12-24

申请号：US12309762

申请日：2006-08-03

申请人： Peter James Aldworth ,  Daren Croxford

发明人： Peter James Aldworth ,  Daren Croxford

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G06F12/0653 ,  G06F12/06

摘要： A data processing system is provided with a memory controller (130) converting memory addresses (170) into selecting signals (120) for a memory device (100). The mapping between memory addresses and selecting signals is provided by mapping logic (140) within the memory device. The configuration of the mapping logic, also known as a mapping scheme, is defined by data stored in mapping specifying data storage (150), which may be altered by operating system software or application software (160) running on the system. Altering this configuration may be as a result of signals received from a monitoring unit (135) which monitors the efficiency with which the current mapping scheme is accessing data stored in the memory device. More than one mapping scheme may be used within a single memory device.

摘要翻译： 数据处理系统具有将存储器地址（170）转换为用于存储器件（100）的选择信号（120）的存储器控​​制器（130）。 存储器地址和选择信号之间的映射由存储器件内的映射逻辑（140）提供。 映射逻辑（也称为映射方案）的配置由存储在映射指定数据存储器（150）中的数据定义，映射逻辑可以通过在系统上运行的操作系统软件或应用软件（160）来改变。 改变该配置可以是由监视单元（135）接收的信号的结果，监控单元（135）监视当前映射方案正在访问存储在存储设备中的数据的效率。 可以在单个存储器件内使用多于一个的映射方案。

公开(公告)号：US07822926B2

公开(公告)日：2010-10-26

申请号：US11785140

申请日：2007-04-16

申请人： Daren Croxford ,  Peter James Aldworth

发明人： Daren Croxford ,  Peter James Aldworth

IPC分类号： G06F13/00

CPC分类号： G06F12/1027 ,  G06F12/0886

摘要： A data processor includes a cache memory having a plurality of cache rows each row storing a cache line of data values, a memory management unit responsive to a page table entry to control access to a corresponding group of memory addresses forming a memory page, and a cache controller coupled to said cache memory and responsive to a cache miss to trigger a line fill operation to store data values into a cache row. The cache controller is responsive to a cache line size specifier associated with at least one page table entry to vary the number of data values within a cache line fetched in a line fill operation in dependence upon said cache line size specifier. Controlling cache line size on a page basis is more efficient than controlling cache line size on a cache row or virtual address basis.

摘要翻译： 数据处理器包括具有多个高速缓存行的高速缓冲存储器行，每行存储数据值的高速缓存行，响应于页表条目的存储器管理单元，以控制访问形成存储器页的相应组的存储器地址，以及 高速缓存控制器耦合到所述高速缓冲存储器并且响应于高速缓存未命中以触发线填充操作以将数据值存储到高速缓存行中。 缓存控制器响应于与至少一个页表项相关联的高速缓存行大小说明符，以根据所述高速缓存行大小说明符改变在行填充操作中取出的高速缓存行内的数据值的数量。 以缓存行或虚拟地址为基础，控制高速缓存线路大小比基于页面更高效。

公开(公告)号：US20090287865A1

公开(公告)日：2009-11-19

申请号：US12086244

申请日：2005-12-22

申请人： Peter James Aldworth ,  Andrew Benson ,  Daren Croxford

发明人： Peter James Aldworth ,  Andrew Benson ,  Daren Croxford

IPC分类号： G06F13/00

CPC分类号： G06F13/362 ,  G06F13/1626

摘要： A method, an interconnect and a system for processing data is disclosed. The method comprises the steps of: a) receiving a request to perform a data transaction between a master unit and a slave unit, b) receiving an indication of a quality of service requirement associated with said data transaction; c) determining an interconnect quality of service level achievable when transmitting said data transaction over the interconnect logic having regard to any other pending data transactions which are yet to be issued; d) determining a slave quality of service level achievable when responding to said data transaction once received by said slave unit from said interconnect logic; and e) determining whether the combined interconnect quality of service level and the slave quality of service level fails to achieve the quality of service requirement and, if so, reordering the pending data transactions to enable the quality of service requirement of each data transaction to be achieved. Hence, arbitration between data transactions occurs prior to those transactions being provided to the interconnect. It will be appreciated that this enables pending data transactions to be systematically reordered and the quality of service level for each of these reordered data transactions to be accurately calculated to ensure that the quality of service requirement for each of those data transactions is achieved. Accordingly, this enables all aspects of quality of service to be budgeted together and true end-to-end quality of service may be determined for each data transaction.

摘要翻译： 公开了一种用于处理数据的方法，互连和系统。 该方法包括以下步骤：a）接收在主单元和从单元之间执行数据交易的请求，b）接收与所述数据交易相关联的服务质量要求的指示; c）确定在考虑到尚未发布的任何其他未决数据事务时在互连逻辑上传输所述数据事务时可实现的服务级别的互连质量; d）当响应所述从属单元从所述从属单元接收到的所述数据事务从所述互连逻辑时，确定可实现的从服务质量水平; 以及e）确定组合的互连服务质量水平和从服务质量水平是否不能实现服务质量要求，如果是，则重新排序待处理的数据交易，以使得每个数据交易的服务质量要求是 实现了 因此，数据事务之间的仲裁发生在提供给互连的事务之前。 应当理解，这使得能够系统地重新排序待处理的数据事务，并且可以精确地计算这些重新排序的数据事务中的每一个的服务质量水平，以确保实现每个数据事务的服务质量要求。 因此，这使得服务质量的所有方面能够被预算在一起，并且可以为每个数据交易确定真实的端到端的服务质量。

公开(公告)号：US07089393B2

公开(公告)日：2006-08-08

申请号：US10042354

申请日：2002-01-11

申请人： Paul Matthew Carpenter ,  Peter James Aldworth

发明人： Paul Matthew Carpenter ,  Peter James Aldworth

IPC分类号： G06F12/04

CPC分类号： G06F13/4217

摘要： A data processing system using a main processor 8 and a coprocessor 10 provides coprocessor load instructions (USALD) for loading a variable number of data values dependent upon alignment into the coprocessor 10 and also specifying data processing operations to be performed upon operands within those loaded data words to generate result data words. The specified coprocessor processing operations may be a sum of absolute differences calculation for a row of pixel byte values. The result of this may be accumulated within an accumulate register 22. A coprocessor memory 18 is provided within the coprocessor 10 to provide local storage of frequently used operand values for the coprocessor 10.

摘要翻译： 使用主处理器8和协处理器10的数据处理系统提供协处理器加载指令（USALD），用于将取决于对准的可变数量的数据值加载到协处理器10中，并且还指定要对这些加载的数据内的操作数执行的数据处理操作 生成结果数据字的单词。 指定的协处理器处理操作可以是像素字节值行的绝对差计算的和。 其结果可以积累在累积寄存器22内。 在协处理器10内提供协处理器存储器18，以便为协处理器10提供经常使用的操作数值的本地存储。

公开(公告)号：US08108596B2

公开(公告)日：2012-01-31

申请号：US12309762

申请日：2006-08-03

申请人： Peter James Aldworth ,  Daren Croxford

发明人： Peter James Aldworth ,  Daren Croxford

IPC分类号： G06F13/00

CPC分类号： G06F12/0653 ,  G06F12/06

摘要： A data processing system is provided with a memory controller (130) converting memory addresses (170) into selecting signals (120) for a memory device (100). The mapping between memory addresses and selecting signals is provided by mapping logic (140) within the memory device. The configuration of the mapping logic, also known as a mapping scheme, is defined by data stored in mapping specifying data storage (150), which may be altered by operating system software or application software (160) running on the system. Altering this configuration may be as a result of signals received from a monitoring unit (135) which monitors the efficiency with which the current mapping scheme is accessing data stored in the memory device. More than one mapping scheme may be used within a single memory device.

摘要翻译： 数据处理系统具有将存储器地址（170）转换为用于存储器件（100）的选择信号（120）的存储器控​​制器（130）。 存储器地址和选择信号之间的映射由存储器件内的映射逻辑（140）提供。 映射逻辑（也称为映射方案）的配置由存储在映射指定数据存储器（150）中的数据定义，映射逻辑可以通过在系统上运行的操作系统软件或应用软件（160）来改变。 改变该配置可以是由监视单元（135）接收的信号的结果，监控单元（135）监视当前映射方案正在访问存储在存储设备中的数据的效率。 可以在单个存储器件内使用多于一个的映射方案。

公开(公告)号：US07802040B2

公开(公告)日：2010-09-21

申请号：US12086244

申请日：2005-12-22

申请人： Peter James Aldworth ,  Andrew Benson ,  Daren Croxford

发明人： Peter James Aldworth ,  Andrew Benson ,  Daren Croxford

IPC分类号： G06F13/362 ,  G06F13/372 ,  G06F13/34

CPC分类号： G06F13/362 ,  G06F13/1626

摘要： A method, an interconnect and a system for processing data is disclosed. The method comprises the steps of: a) receiving a request to perform a data transaction between a master unit and a slave unit, b) receiving an indication of a quality of service requirement associated with said data transaction; c) determining an interconnect quality of service level achievable when transmitting said data transaction over the interconnect logic having regard to any other pending data transactions which are yet to be issued; d) determining a slave quality of service level achievable when responding to said data transaction once received by said slave unit from said interconnect logic; and e) determining whether the combined interconnect quality of service level and the slave quality of service level fails to achieve the quality of service requirement and, if so, reordering the pending data transactions to enable the quality of service requirement of each data transaction to be achieved. Hence, arbitration between data transactions occurs prior to those transactions being provided to the interconnect. It will be appreciated that this enables pending data transactions to be systematically reordered and the quality of service level for each of these reordered data transactions to be accurately calculated to ensure that the quality of service requirement for each of those data transactions is achieved. Accordingly, this enables all aspects of quality of service to be budgeted together and true end-to-end quality of service may be determined for each data transaction.

摘要翻译： 公开了一种用于处理数据的方法，互连和系统。 该方法包括以下步骤：a）接收在主单元和从单元之间执行数据交易的请求，b）接收与所述数据交易相关联的服务质量要求的指示; c）确定在考虑到尚未发布的任何其他未决数据事务时在互连逻辑上传输所述数据事务时可实现的服务级别的互连质量; d）当响应所述从属单元从所述从属单元接收到的所述数据事务从所述互连逻辑时，确定可实现的从服务质量水平; 以及e）确定组合的互连服务质量水平和从服务质量水平是否不能实现服务质量要求，如果是，则重新排序待处理的数据交易，以使得每个数据交易的服务质量要求是 实现了 因此，数据事务之间的仲裁发生在提供给互连的事务之前。 应当理解，这使得能够系统地重新排序待处理的数据事务，并且可以精确地计算这些重新排序的数据事务中的每一个的服务质量水平，以确保实现每个数据事务的服务质量要求。 因此，这使得服务质量的所有方面能够被预算在一起，并且可以为每个数据交易确定真实的端到端的服务质量。

公开(公告)号：US20080256303A1

公开(公告)日：2008-10-16

申请号：US11785140

申请日：2007-04-16

申请人： Daren Croxford ,  Peter James Aldworth

发明人： Daren Croxford ,  Peter James Aldworth

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/0886

摘要： An apparatus for processing data comprises a cache memory having a plurality of cache rows each operable to store a cache line of data values, a memory management unit responsive to a page table entry to control access to a corresponding group of memory addresses forming a memory page, and a cache controller coupled to said cache memory and responsive to a cache miss to trigger a line fill operation to store data values into a cache row. The cache controller is responsive to a cache line size specifier associated with at least one page table entry to vary the number of data values within a cache line fetched in a line fill operation in dependence upon said cache line size specifier. Accordingly, by associating cache line size specifiers with page table entries, the number of data values to be stored in a line fill operation can be controlled on a memory page basis, which is advantageous because data values within the same page of memory are likely to be subject to similar types of access behaviour in the cache. Additionally, controlling cache line size on a page basis is more efficient, in terms of computation and storage, than controlling cache line size on a cache row or virtual address basis.

摘要翻译： 一种用于处理数据的装置包括具有多个高速缓存行的高速缓存存储器，每个高速缓冲存储器行可存储数据值的高速缓存线，响应于页表条目的存储器管理单元，以控制访问构成存储器页的相应组的存储器地址 以及高速缓存控制器，其耦合到所述高速缓存存储器并且响应于高速缓存未命中以触发线填充操作以将数据值存储到高速缓存行中。 缓存控制器响应于与至少一个页表项相关联的高速缓存行大小说明符，以根据所述高速缓存行大小说明符改变在行填充操作中取出的高速缓存行内的数据值的数量。 因此，通过将高速缓存行大小说明符与页表项相关联，可以在存储器页面的基础上控制要存储在行填充操作中的数据值的数量，这是有利的，因为存储器的同一页内的数据值可能 在缓存中受到类似类型的访问行为的影响。 此外，与控制高速缓存行或虚拟地址上的高速缓存行大小相比，在计算和存储方面，基于页面控制高速缓存行大小更为有效。

公开(公告)号：US06760798B1

公开(公告)日：2004-07-06

申请号：US09616067

申请日：2000-07-13

申请人： Peter James Aldworth

发明人： Peter James Aldworth

IPC分类号： G06F13362

CPC分类号： G06F1/14

摘要： The present invention relates to an interface mechanism and particularly to an interface mechanism for interfacing a real-time clock operating at a first frequency with a data processing circuit operating at a second frequency. The interface mechanism comprises a first input for receiving a relative real-time clock value from the real-time clock, and a second input for receiving an update value from the data processing circuit specifying a desired value for the real-time clock. Update logic is also provided for producing an absolute real-time clock value, the update logic being arranged in response to receipt of the update value to generate an offset value derived from the relative real-time clock value and the update value, the offset value then being applied to the relative real-time clock value to produce an updated absolute real-time clock value. The updated absolute real-time clock value is then output from the interface mechanism. This enables the update of the real-time clock to be performed very efficiently, without the need to perform any of the update procedure in the slow frequency domain of the real-time clock.

摘要翻译： 本发明涉及一种接口机制，特别涉及一种用于将以第一频率操作的实时时钟与以第二频率工作的数据处理电路接口​​的接口机构。 接口机构包括用于从实时时钟接收相对实时时钟值的第一输入端和用于从指定实时时钟的期望值的数据处理电路接收更新值的第二输入端。 还提供更新逻辑用于产生绝对实时时钟值，更新逻辑响应于接收到更新值被安排以生成从相对实时时钟值和更新值导出的偏移值，偏移值 然后施加到相对实时时钟值以产生更新的绝对实时时钟值。 然后从接口机制输出更新的绝对实时时钟值。 这使得能够非常有效地执行实时时钟的更新，而不需要在实时时钟的低频域中执行任何更新过程。

公开(公告)号：US5935197A

公开(公告)日：1999-08-10

申请号：US824015

申请日：1997-03-21

申请人： Peter James Aldworth

发明人： Peter James Aldworth

IPC分类号： G06F7/48 ,  G06F7/52 ,  G06F7/533 ,  G06F15/80

CPC分类号： G06F7/48 ,  G06F15/8007 ,  G06F2207/382 ,  G06F7/5338

摘要： The present invention provides a data processing circuit and method for performing arithmetic processing on data signals input to the circuit, comprising: a plurality of input terminals for receiving a plurality of data signals to be processed; a plurality of interconnected arithmetic processing units, one corresponding to each input terminal, for processing the data signals received at the corresponding input terminal; and a selector for routing the data signals at said input terminals to the corresponding arithmetic processing units in a first mode of operation, or for routing a selected one of said data signals to said plurality of arithmetic processing units in a second mode of operation; whereby, in said first mode of operation, data signals arriving at said input terminals are processed in parallel by said corresponding arithmetic processing units, and, in said second mode of operation, at any point in time, one of said data signals is processed by said plurality of arithmetic processing units. By this approach, the data processing circuit is provided with two modes of operation, the first mode of operation corresponding to a fast, reduced precision mode of operation, whilst the second mode of operation corresponds to a slower but higher precision mode of operation. The same hardware is reused for both modes of operation, thereby reducing the hardware requirements and so enabling the circuit to be relatively small.

摘要翻译： 本发明提供了一种用于对输入到电路的数据信号执行算术处理的数据处理电路和方法，包括：多个用于接收要处理的多个数据信号的输入端; 多个相互连接的运算处理单元，一个对应于每个输入端，用于处理在相应输入端接收的数据信号; 以及选择器，用于在第一操作模式下将所述输入端处的数据信号路由到相应的算术处理单元，或者用于在第二操作模式中将所选数据信号路由到所述多个运算处理单元; 由此，在所述第一操作模式中，到达所述输入端的数据信号由所述对应的运算处理单元并行处理，并且在所述第二操作模式中，在任何时间点，所述数据信号中的一个被处理 所述多个算术处理单元。 通过这种方法，数据处理电路具有两种操作模式，第一操作模式对应于快速，精确的精确操作模式，而第二操作模式对应于较慢但较高精度的操作模式。 对于这两种操作模式，相同的硬件被重复使用，从而降低硬件要求，并且使电路相对较小。