Access control in a data processing apparatus
    1.
    发明授权
    Access control in a data processing apparatus 有权
    数据处理装置中的访问控制

    公开(公告)号:US07149862B2

    公开(公告)日:2006-12-12

    申请号:US10933478

    申请日:2004-09-03

    IPC分类号: G06F12/00

    CPC分类号: G06F12/1441

    摘要: A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request. Further, access control logic is provided which is associated with the slave device, the access control logic being operable to receive the access request from the bus and an indication of the partition from the control storage and, if the access request is a non-secure access request, to prevent access to the secure region.

    摘要翻译: 提供了一种用于控制对从设备的访问的数据处理设备和方法,该从设备具有与之相关联的地址范围。 该装置包括可编程的控制存储器,用于定义识别地址范围中的安全区域和非安全区域的分区,数据处理设备支持包括安全模式的多种操作模式,并且控制存储器仅可由 软件在安全模式下执行。 主设备被布置为在总线上发出访问请求,该访问请求标识地址范围内的一系列地址,并且包括指示该访问请求是安全访问请求还是非安全访问请求的控制信号。 安全区域只能通过安全访问请求访问。 此外,提供与从设备相关联的访问控制逻辑,访问控制逻辑可操作以从总线接收访问请求以及来自控制存储器的分区的指示,以及如果访问请求是非安全的 访问请求,以防止访问安全区域。

    Control of access to a memory by a device
    5.
    发明授权
    Control of access to a memory by a device 有权
    控制设备对存储器的访问

    公开(公告)号:US07305534B2

    公开(公告)日:2007-12-04

    申请号:US10714561

    申请日:2003-11-17

    IPC分类号: G06F12/00

    摘要: The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the present invention, the data processing apparatus further comprises partition checking logic coupled to the device bus and operable whenever the memory access request as issued by the device pertains to the non-secure domain, to detect if the memory access request is seeking to access the secure memory and upon such detection to prevent the access specified by that memory request. This approach significantly improves the security of data contained within a secure portion of memory.

    摘要翻译: 本发明提供一种用于控制对存储器的访问的数据处理装置和方法。 数据处理装置具有安全域和非安全域,在安全域中,数据处理装置具有对非安全域中不可访问的安全数据的访问。 数据处理装置包括经由设备总线耦合到存储器的设备,并且当设备需要存储器中的数据项时,可以向设备总线发出存储器访问请求,该存储器访问请求涉及安全域或 非安全域。 存储器可操作以存储设备所需的数据,并且包含用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器。 根据本发明,数据处理装置还包括耦合到设备总线的分区检查逻辑,每当由设备发布的存储器访问请求与非安全域相关时,可操作,以检测存储器访问请求是否正在寻找 以访问安全存储器并且在这种检测时防止由该存储器请求指定的访问。 这种方法显着提高了包含在存储器安全部分内的数据的安全性。

    Vectored interrupt control within a system having a secure domain and a non-secure domain
    7.
    发明授权
    Vectored interrupt control within a system having a secure domain and a non-secure domain 有权
    具有安全域和非安全域的系统内的向量中断控制

    公开(公告)号:US07117284B2

    公开(公告)日:2006-10-03

    申请号:US10714562

    申请日:2003-11-17

    IPC分类号: G06F13/24

    CPC分类号: G06F9/4812

    摘要: A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.

    摘要翻译: 数据处理装置可以以多种模式操作,也可以在安全域或非安全域中操作。 当在安全域内以安全模式操作时,程序可以访问当处理器以非安全模式操作时无法访问的安全数据。 提供向量中断控制器以响应于发生除了条件而产生异常处理程序地址。 向量中断控制器是可编程的,参数指定每个异常情况是否应触发安全或非安全域中的异常处理程序,如果在适当的域中发生异常,则使用异常处理程序地址。 向量中断控制器还包括指定域切换异常处理程序地址的参数,以便在处理器不在适当域中时发生异常情况时使用。

    Technique for accessing memory in a data processing apparatus
    8.
    发明授权
    Technique for accessing memory in a data processing apparatus 有权
    用于访问数据处理设备中的存储器的技术

    公开(公告)号:US07185159B2

    公开(公告)日:2007-02-27

    申请号:US10714520

    申请日:2003-11-17

    IPC分类号: G06F12/00

    摘要: The present invention provides a data processing apparatus and method for accessing memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled via a device bus with the memory, the device being operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the invention, the memory access request as issued by the device includes a domain signal identifying whether the memory access request pertains to either the secure domain or the non-secure domain. The presence of this domain signal issued as part of the memory access request enables checking to be performed to ensure that secure data within the secure memory is not accessed by the device when the memory access request pertains to the non-secure domain.

    摘要翻译: 本发明提供一种访问存储器的数据处理装置和方法。 数据处理装置具有安全域和非安全域,在安全域中,数据处理装置具有对非安全域中不可访问的安全数据的访问。 数据处理设备包括经由设备总线与存储器耦合的设备,当设备需要存储器中的数据项时,该设备可操作地向设备总线发出与安全性相关的存储器访问请求 域或非安全域。 存储器可操作以存储设备所需的数据,并且包含用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器。 根据本发明,由设备发布的存储器访问请求包括识别存储器访问请求是否属于安全域或非安全域的域信号。 作为存储器访问请求的一部分而发布的该域信号的存在使得能够执行检查,以便当存储器访问请求与非安全域相关时,确保安全存储器内的安全数据不被设备访问。

    Diagnostic data capture control for multi-domain processors
    9.
    发明授权
    Diagnostic data capture control for multi-domain processors 有权
    多域处理器的诊断数据捕获控制

    公开(公告)号:US08082589B2

    公开(公告)日:2011-12-20

    申请号:US10714178

    申请日:2003-11-17

    IPC分类号: H04N7/16

    CPC分类号: G06F21/71 G06F2221/2105

    摘要: There is provided a processor operable in a first domain and a second domain, the processor comprising: monitoring logic operable to monitor the processor and capture diagnostic data; a storage element operable to contain at least one control parameter; control logic operable to control the monitoring logic in dependence on the at least one control parameter and the domain in which the processor is operating, to suppress capturing of diagnostic data relating to predetermined activities of the processor in the first domain. In some embodiments the first domain is a secure domain and the second domain is a non-secure domain, the monitoring function being debug or trace.

    摘要翻译: 提供了可在第一域和第二域中操作的处理器,所述处理器包括:监视逻辑,可操作以监视处理器并捕获诊断数据; 存储元件,其可操作以包含至少一个控制参数; 控制逻辑可操作以根据所述至少一个控制参数和所述处理器在其中操作的所述域来控制所述监视逻辑,以抑制与所述第一域中的所述处理器的预定活动有关的诊断数据的捕获。 在一些实施例中,第一域是安全域,而第二域是非安全域,监视功能是调试或跟踪。

    Cache Management Within A Data Processing Apparatus
    10.
    发明申请
    Cache Management Within A Data Processing Apparatus 有权
    数据处理装置内的缓存管理

    公开(公告)号:US20100235579A1

    公开(公告)日:2010-09-16

    申请号:US12223173

    申请日:2006-09-18

    IPC分类号: G06F12/08 G06F12/00

    CPC分类号: G06F12/127 G06F12/0862

    摘要: A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.

    摘要翻译: 提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。 数据处理装置具有用于执行指令序列的至少一个处理单元,每个这样的处理单元具有与其相关联的高速缓冲存储器,每个高速缓冲存储器具有多个高速缓存行,用于存储由相关联的处理单元执行访问时的数据值 指令序列 提供了识别逻辑,对于每个高速缓存来说,监视数据处理装置内的数据业务,并且基于此,生成用于驱逐的标识的优选,以便识别为驱逐优选的一个或多个数据值。 然后,对于每个高速缓存,缓存维护逻辑被设置为实现高速缓存维护操作,在该高速缓存维护操作期间,考虑到存储的数据值的识别逻辑生成的用于逐出识别​​的任何优选的执行,从该高速缓存中选择一个或多个数据值 在那个缓存中。 已经发现,这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。