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公开(公告)号：US07466647B2
公开(公告)日：2008-12-16
申请号：US11054287
申请日：2005-02-09
申请人： Andrew James Bianchi , Eric Jason Fluhr , Masood Ahmed Khan , Michael Ju Hyeok Lee , Edelmar Seewann
发明人： Andrew James Bianchi , Eric Jason Fluhr , Masood Ahmed Khan , Michael Ju Hyeok Lee , Edelmar Seewann
CPC分类号： G06F13/4018 , G11C7/1006
摘要： A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.
摘要翻译： 一种使用2：1 MUX来控制存储器阵列中的读访问，数据旁路和页大小旁路的方法和装置。 本发明的机制将通常需要的3：1 MUX将这三个功能管理到2：1 MUX。
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2.发明授权Multifunctional latch circuit for use with both SRAM array and self test device 失效多功能锁存电路，用于SRAM阵列和自检装置公开(公告)号：US07099201B1
公开(公告)日：2006-08-29
申请号：US11055043
申请日：2005-02-10
申请人： Andrew James Bianchi , Yuen Hung Chan , William Vincent Huott , Michael Ju Hyeok Lee , Edelmar Seewann , Philip George Shephard, III
发明人： Andrew James Bianchi , Yuen Hung Chan , William Vincent Huott , Michael Ju Hyeok Lee , Edelmar Seewann , Philip George Shephard, III
IPC分类号： G11C7/10
CPC分类号： G11C29/1201 , G11C11/41 , G11C11/419 , G11C29/12
摘要： An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.
摘要翻译： 提供了一种在单个锁存电路中组合自检和功能特征的装置和方法，其可以与SRAM阵列一起使用，并且被有效地实现为L1-L2锁存器。 在从SRAM阵列的部分写入期间，未知状态的数据位被禁止进入锁存电路，而用于测试的数据被允许进入。 在本发明的一个有用的实施例中，锁存电路与提供模式选择信号的模式控制一起使用，以便以至少全写和部分写模式的多种模式之一来操作锁存电路。 锁存电路还包括数据保持电路，用于选择性地接收和存储耦合到锁存电路的数据。 响应于模式选择信号的第一使能电路使得保持电路能够在完全写入模式期间接收包含在阵列中的所有数据，并且还允许保持电路仅在部分时钟期间仅接收阵列中包含的一些数据位 写模式。
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公开(公告)号：US07471103B2
公开(公告)日：2008-12-30
申请号：US11567581
申请日：2006-12-06
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G11C15/00
摘要： A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.
摘要翻译： 描述了在存储器阵列内实现复杂逻辑的逻辑门。 逻辑门在第一输入电路和第二输入电路处接收第一存储单元信号，第二存储单元信号，第一外部信号或第二外部信号中的至少三个。 然后逻辑门使用第一存储单元信号，第二存储单元信号，第一外部信号或第二外部信号执行一组逻辑功能中的一个。 该组逻辑功能包括匹配功能，OR-AND功能或AND功能中的至少一个。
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4.发明申请公开(公告)号：US20090027079A1
公开(公告)日：2009-01-29
申请号：US12250917
申请日：2008-10-14
IPC分类号： H03K19/173
CPC分类号： G11C15/00
摘要： A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.
摘要翻译： 描述了在存储器阵列内实现复杂逻辑的逻辑门。 逻辑门在第一输入电路和第二输入电路处接收第一存储单元信号，第二存储单元信号，第一外部信号或第二外部信号中的至少三个。 然后，逻辑门使用第一存储单元信号，第二存储单元信号，第一外部信号或第二外部信号执行一组逻辑功能中的一个。 该组逻辑功能包括匹配功能，OR-AND功能或AND功能中的至少一个。
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5.发明授权公开(公告)号：US07683662B2
公开(公告)日：2010-03-23
申请号：US12250917
申请日：2008-10-14
IPC分类号： G06F7/31 , H03K19/173
CPC分类号： G11C15/00
摘要： A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.
摘要翻译： 描述了在存储器阵列内实现复杂逻辑的逻辑门。 逻辑门在第一输入电路和第二输入电路处接收第一存储单元信号，第二存储单元信号，第一外部信号或第二外部信号中的至少三个。 然后逻辑门使用第一存储单元信号，第二存储单元信号，第一外部信号或第二外部信号执行一组逻辑功能中的一个。 该组逻辑功能包括匹配功能，OR-AND功能或AND功能中的至少一个。
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6.发明申请公开(公告)号：US20080136447A1
公开(公告)日：2008-06-12
申请号：US11567581
申请日：2006-12-06
IPC分类号： H03K19/177
CPC分类号： G11C15/00
摘要： A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.
摘要翻译： 描述了在存储器阵列内实现复杂逻辑的逻辑门。 逻辑门在第一输入电路和第二输入电路处接收第一存储单元信号，第二存储单元信号，第一外部信号或第二外部信号中的至少三个。 然后逻辑门使用第一存储单元信号，第二存储单元信号，第一外部信号或第二外部信号执行一组逻辑功能中的一个。 该组逻辑功能包括匹配功能，OR-AND功能或AND功能中的至少一个。
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7.发明授权Method and apparatus which implements a multi-ported LRU in a multiple-clock system 失效在多时钟系统中实现多端口LRU的方法和装置公开(公告)号：US07085896B2
公开(公告)日：2006-08-01
申请号：US10427135
申请日：2003-04-30
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/0853
摘要： An apparatus for implementing a least-recently used (LRU) mechanism in a multi-port cache memory includes an LRU array and a shift decoder. The LRU array has multiple entries. The shift decoder includes a shifting means for shifting the entries within the LRU array. The shifting means shifts a current one of the entries and adjacent entries once, and loading new address, in response to a single cache hit in the current one of the entries. The shifting means shifts a current one of the entries and adjacent entries once, and loading an address of only one of multiple requesters into the most-recently used (MRU) entry, in response to multiple cache hits in the current one of the entries. The shifting means shifts all subsequent entries, including the current entries, n times, and loading addresses of all requesters contributed to the multiple cache hits in consecutive entries into the MRU entry and subsequent entries, in response to multiple cache hits in consecutive entries. The shifting means shifts some of the entries n times, some of the entries n−1 times, etc., and loading addresses of all requesters that have a cache hit in the multiple cache hits into the MRU entry and subsequent entries, in response to multiple cache hits not in the same entry or consecutive entries.
摘要翻译： 用于在多端口高速缓冲存储器中实现最近最少使用（LRU）机制的装置包括LRU阵列和移位解码器。 LRU数组有多个条目。 移位解码器包括用于移位LRU阵列内的条目的移位装置。 移位装置响应于当前一个条目中的单个高速缓存命中，移动条目中的当前条目和相邻条目一次，并加载新地址。 移动装置响应于当前一个条目中的多个高速缓存命中，将当前条目和相邻条目之一移动一次，并将仅一个请求者的地址加载到最近使用的（MRU）条目中。 响应于连续条目中的多个高速缓存命中，移位装置将所有后续条目（包括当前条目）n次以及向连续条目中的多个高速缓存命中加载到MRU条目和后续条目中的所有请求者的加载地址。 移动装置将一些条目移动n次，一些条目n-1次等，并且在多个高速缓存中具有高速缓存命中的所有请求者的加载地址命中到MRU条目和后续条目中，以响应于 多个缓存命中不在同一条目或连续条目中。
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