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6 条记录 (耗时 0.019 秒)

    Phase comparator for extending capture range
    1.
    发明授权
    Phase comparator for extending capture range 失效
    相位比较器可扩展捕获范围

    公开(公告)号：US4819081A

    公开(公告)日：1989-04-04

    申请号：US92477

    申请日：1987-09-03

    申请人： Andrew M. Volk ,  Terry L. Baucom ,  Roger Van Brunt

    发明人： Andrew M. Volk ,  Terry L. Baucom ,  Roger Van Brunt

    IPC分类号： H03D13/00 ,  H03L7/10 ,  H03D3/02

    CPC分类号： H03L7/10 ,  H03D13/004

    摘要： An extended range logic circuit is activated to decrease the settling time and prevent slip, when phase difference of two signals being compared by a phase comparator reaches a slip point. The circuit provides error correction signals to compensate for the phase correction at a much faster rate when the phase error reaches a predetermined point, which is proximate to the slip point. However, the extended capture range circuit in only active during the lock acquisition. After lock is achieved the extended capture range logic is disabled, to provide better jitter performance.

    摘要翻译： 当相位比较器比较两个信号的相位差达到滑点时，扩展范围逻辑电路被激活以减小建立时间并防止滑动。 当相位误差达到接近滑点的预定点时，电路提供纠错信号以更快的速率补偿相位校正。 但是，扩展捕捉范围电路只在锁定采集期间有效。 实现锁定后，扩展捕获范围逻辑被禁用，以提供更好的抖动性能。

    Stabilized phase locked loop
    2.
    发明授权
    Stabilized phase locked loop 失效
    稳定的锁相环

    公开(公告)号：US4829258A

    公开(公告)日：1989-05-09

    申请号：US92478

    申请日：1987-09-03

    申请人： Andrew M. Volk ,  Terry L. Baucom ,  Roger V. Brunt

    发明人： Andrew M. Volk ,  Terry L. Baucom ,  Roger V. Brunt

    IPC分类号： H03L1/00 ,  H03L7/07 ,  H03L7/089

    CPC分类号： H03L7/0805 ,  H03L1/00 ,  H03L7/07 ,  H03L7/089

    摘要： A dual loop phase locked loop system having a secondary loop for controlling various circuit, environmental and process variations. The secondary loop is comprised of a phase comparator, a filter, a transconductance amplifier and a one-shot, wherein the output of the one-shot is fed back as an input signal for comparison with a reference signal at the input of the phase comparator. The filter generates a correction voltage which is dependent on the phase difference determined by the phase comparator, and the transconductance amplifier generates a charging current corresponding to the error voltage from the filter, wherein the charging current controls the charging of the input capacitor to the one-shot circuit for determining the duration of the pulse width of the output of the one-shot. The one-shot based loop is inherently stable since there is only one pole near the origin of the S-Plane. The primary loop is comprised of a phase comparator, a filter, a transconductance amplifier and an output means, which is a VCO and a voltage divider. The primary loop provides the actual phased locked loop of an input reference signal, however, it derives compensating analog trim information from the secondary loop. The dynamic characteristics of the primary loop are established by the reference loop, based on the reference clock frequency. Further, the loop response is controlled by the reference frequency, and is immune to process, temperature and voltage variations. In addition the loop frequency characteristics can be programmed by adjusting the reference clock.

    摘要翻译： 具有用于控制各种电路，环境和工艺变化的次级回路的双回路锁相环系统。 次级回路由相位比较器，滤波器，跨导放大器和单触发器组成，其中单触发器的输出作为输入信号反馈，用于与相位比较器输入端的参考信号进行比较 。 滤波器产生取决于由相位比较器确定的相位差的校正电压，并且跨导放大器产生与来自滤波器的误差电压相对应的充电电流，其中充电电流控制输入电容器对该充电电流的充电 -shot电路，用于确定单次输出的脉冲宽度的持续时间。 由于在S平面的原点附近只有一个极点，所以基于单次的回路是固有的稳定的。 主回路由相位比较器，滤波器，跨导放大器和作为VCO和分压器的输出装置组成。 主回路提供输入参考信号的实际相位锁定环，然而，它从辅助回路得到补偿模拟微调信息。 基于参考时钟频率，基准回路建立主回路的动态特性。 此外，环路响应由参考频率控制，并且不受处理，温度和电压变化的影响。 此外，可以通过调整参考时钟来编程环路频率特性。

    High speed, low power output circuit with temperature compensated noise control
    3.
    发明授权
    High speed, low power output circuit with temperature compensated noise control 失效
    具有温度补偿噪声控制的高速，低功率输出电路

    公开(公告)号：US5291071A

    公开(公告)日：1994-03-01

    申请号：US881843

    申请日：1992-05-12

    申请人： Michael J. Allen ,  Terry L. Baucom

    发明人： Michael J. Allen ,  Terry L. Baucom

    IPC分类号： H03K19/173 ,  H03K3/01 ,  H03K3/26

    CPC分类号： H03K19/1736 ,  H03K19/1731 ,  H03K19/1737

    摘要： The present invention discloses a semiconductor output circuit with temperature compensated noise control. The output circuit of the present invention presents an increase in speed, a reduction in power consumption, and a reduction in noise level as compared with the prior art temperature compensated noise control output circuits. These advantages are obtained by utilizing the present invention's current control means which current control means is driven by a temperature compensation circuit.

    摘要翻译： 本发明公开了一种具有温度补偿噪声控制的半导体输出电路。 与现有技术的温度补偿噪声控制输出电路相比，本发明的输出电路具有速度的提高，功耗的降低和噪声水平的降低。 这些优点通过利用本发明的电流控制装置获得，电流控制装置由温度补偿电路驱动。

    High speed NOR'ing inverting, MUX'ing and latching circuit with temperature compensated output noise control
    4.
    发明授权
    High speed NOR'ing inverting, MUX'ing and latching circuit with temperature compensated output noise control 失效
    高速NOR转换，多路复用和锁存电路，具有温度补偿输出噪声控制

    公开(公告)号：US5168178A

    公开(公告)日：1992-12-01

    申请号：US752780

    申请日：1991-08-30

    申请人： Michael J. Allen ,  Terry L. Baucom ,  Diana Esmail-Zandi

    发明人： Michael J. Allen ,  Terry L. Baucom ,  Diana Esmail-Zandi

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1736 ,  H03K19/1731 ,  H03K19/1737

    摘要： The present invention discloses an improved two-stage macrocell for Programmable Logic Devices. According to the first stage of the improved circuit of the present invention's macrocell, combined NOR'ing, inverting, MUX'ing, and latching functions are performed by the single first stage. This single stage replaces the prior art multiple stages for performing the same NOR'ing, inverting, MUX'ing, and latching functions of the present invention. Since the present invention replaces the prior art multiple stages with a single stage, the speed of the present invention in performing the above NOR'ing, inverting, MUX'ing, and latching functions is significantly improved over the prior art. Furthermore, the present invention also discloses a second stage for a low-noise temperature-compensated output circuit. According to this aspect of the present invention, the low temperature noise on the ground and the supply voltage lines is reduced so that the low temperature noise approximately equals the high temperature noise on the ground and the supply voltage lines. Moreover, the speed improvement of the first stage of the present invention, described above, compensates for any speed degradation produced by the low-noise temperature-compensated output circuit of the second stage, so that the overall speed of the first and the second stages of the macrocell of the present invention is still improved over the prior art multiple-stage macrocell.

    摘要翻译： 本发明公开了一种用于可编程逻辑器件的改进的两级宏单元。 根据本发明的宏单元的改进电路的第一阶段，由单个第一阶段执行组合NOR，反相，多路复用和锁存功能。 该单级替代了用于执行本发明的相同NOR，反相，多路复用和锁存功能的现有技术的多个级。 由于本发明用单级代替现有技术的多级，所以与现有技术相比，本发明在执行上述NOR，反相，多路复用和锁存功能方面的速度显着提高。 此外，本发明还公开了一种用于低噪声温度补偿输出电路的第二级。 根据本发明的这个方面，降低了地面上的低温噪声和电源电压线，使得低温噪声大致等于地面和电源电压线上的高温噪声。 此外，如上所述的本发明的第一级的速度改进补偿由第二级的低噪声温度补偿输出电路产生的任何速度劣化，使得第一级和第二级的总速度 与现有技术的多级宏小区相比，仍然改进了本发明的宏小区。

    Low power programmable logic arrays
    5.
    发明授权
    Low power programmable logic arrays 失效
    低功耗可编程逻辑阵列

    公开(公告)号：US5576636A

    公开(公告)日：1996-11-19

    申请号：US515248

    申请日：1995-08-15

    申请人： Terry L. Baucom

    发明人： Terry L. Baucom

    IPC分类号： H03K19/177 ,  H03K19/094

    CPC分类号： H03K19/17708

    摘要： A programmable logic array including a plurality of AND gates for providing product terms, a plurality of OR gates connected to receive the product terms for providing output signals, and circuitry for reducing power dissipation caused by the application of clock signals to the programmable logic array.

    摘要翻译： 包括用于提供产品项的多个与门的可编程逻辑阵列，连接以接收用于提供输出信号的乘积项的多个或门，以及用于减少由可编程逻辑阵列施加时钟信号引起的功耗的电路。