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    Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same
    5.
    发明授权
    Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same 有权
    具有嵌入式拉伸应变层的晶体管，其具有减小的偏移到栅电极的方法及其形成方法

    公开(公告)号：US07659213B2

    公开(公告)日：2010-02-09

    申请号：US11566840

    申请日：2006-12-05

    申请人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    发明人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    IPC分类号： H01L21/31 ,  H01L21/42 ,  H01L21/8222

    CPC分类号： C23C8/20 ,  C23C8/80 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    摘要： By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing mechanism. The carbon implantation may be preceded by a pre-amorphization implantation, for instance on the basis of silicon. Moreover, by removing a spacer structure used for forming deep drain and source regions, the degree of lateral offset of the strained silicon/carbon material with respect to the gate electrode may be determined substantially independently from other process requirements. Moreover, an additional sidewall spacer used for forming metal silicide regions may be provided with reduced permittivity, thereby additionally contributing to an overall performance enhancement.

    摘要翻译： 通过离子注入和随后的基于闪光或基于激光的退火工艺引入碳，具有拉伸应变的应变硅/碳材料可以紧邻通道区域定位，从而增强应变诱导机制。 可以在碳注入之前进行预非晶化注入，例如基于硅。 此外，通过去除用于形成深漏极和源极区的间隔结构，应变硅/碳材料相对于栅极的横向偏移程度可以基本上独立于其它工艺要求来确定。 此外，用于形成金属硅化物区域的附加侧壁间隔物可以具有降低的介电常数，从而另外有助于整体性能提高。

    Technique for providing multiple stress sources in NMOS and PMOS transistors
    9.
    发明授权
    Technique for providing multiple stress sources in NMOS and PMOS transistors 有权
    在NMOS和PMOS晶体管中提供多个应力源的技术

    公开(公告)号：US07329571B2

    公开(公告)日：2008-02-12

    申请号：US11466802

    申请日：2006-08-24

    申请人： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

    发明人： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

    IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/44

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684

    摘要： By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.

    摘要翻译： 通过在不同类型的晶体管中组合多个应力诱导机构，可以获得显着的性能增益，从而在调整产品特定特性方面提供增强的灵活性。 为此，可以在PMOS和NMOS晶体管上通常形成具有高拉伸应力的侧壁间隔物，其中可以通过相应的压缩应力接触蚀刻停止层补偿对PMOS晶体管的有害影响，而NMOS晶体管包括接触蚀刻 停止层拉伸应力。 此外，PMOS晶体管包括用于在沟道区域中有效地产生压缩应变的嵌入式应变半导体层。

    TECHNIQUE FOR PROVIDING MULTIPLE STRESS SOURCES IN NMOS AND PMOS TRANSISTORS
    10.
    发明申请
    TECHNIQUE FOR PROVIDING MULTIPLE STRESS SOURCES IN NMOS AND PMOS TRANSISTORS 有权
    在NMOS和PMOS晶体管中提供多个应力源的技术

    公开(公告)号：US20070096195A1

    公开(公告)日：2007-05-03

    申请号：US11466802

    申请日：2006-08-24

    申请人： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

    发明人： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684

    摘要： By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.

    摘要翻译： 通过在不同类型的晶体管中组合多个应力诱导机构，可以获得显着的性能增益，从而在调整产品特定特性方面提供增强的灵活性。 为此，可以在PMOS和NMOS晶体管上通常形成具有高拉伸应力的侧壁间隔物，其中可以通过相应的压缩应力接触蚀刻停止层补偿对PMOS晶体管的有害影响，而NMOS晶体管包括接触蚀刻 停止层拉伸应力。 此外，PMOS晶体管包括用于在沟道区域中有效地产生压缩应变的嵌入式应变半导体层。