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公开(公告)号：US07535918B2
公开(公告)日：2009-05-19
申请号：US11171602
申请日：2005-06-30
CPC分类号： G06F13/423
摘要： In one embodiment, a data movement module (DMM) may receive a command to copy data from a source buffer to a destination buffer. One or more cache lines corresponding to addresses of the source buffer and the destination buffer may be invalidated. Also, an entry may be added to a queue to indicate that the command to copy is completion pending.
摘要翻译： 在一个实施例中，数据移动模块（DMM）可以接收将数据从源缓冲器复制到目的地缓冲器的命令。 对应于源缓冲器和目的地缓冲器的地址的一个或多个高速缓存行可能被无效。 此外，可以将一个条目添加到队列中，以指示要复制的命令是待完成的。
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公开(公告)号：US20070156960A1
公开(公告)日：2007-07-05
申请号：US11323793
申请日：2005-12-30
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： Methods and apparatus to reduce the number of uncacheable write requests are described. In one embodiment, a single uncacheable write request is sent instead of a plurality of uncacheable write requests to an address.
摘要翻译： 描述减少不可写入写入请求数量的方法和装置。 在一个实施例中，单个不可缓存的写入请求被发送而不是多个不可缓存的写入请求到地址。
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公开(公告)号：US20070002881A1
公开(公告)日：2007-01-04
申请号：US11171602
申请日：2005-06-30
申请人： Anil Vasudevan , D. Bell , Sujoy Sen , Parthasarathy Sarangam
发明人： Anil Vasudevan , D. Bell , Sujoy Sen , Parthasarathy Sarangam
IPC分类号： H04L12/28
CPC分类号： G06F13/423
摘要： In one embodiment, a data movement module (DMM) may receive a command to copy data from a source buffer to a destination buffer. One or more cache lines corresponding to addresses of the source buffer and the destination buffer may be invalidated. Also, an entry may be added to a queue to indicate that the command to copy is completion pending.
摘要翻译： 在一个实施例中，数据移动模块（DMM）可以接收将数据从源缓冲器复制到目的地缓冲器的命令。 对应于源缓冲器和目的地缓冲器的地址的一个或多个高速缓存行可能被无效。 此外，可以将一个条目添加到队列中，以指示要复制的命令是待完成的。
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4.发明申请DUAL INTERFACE COHERENT AND NON-COHERENT NETWORK INTERFACE CONTROLLER ARCHITECTURE 审中-公开双界面相关和非关联网络接口控制器架构公开(公告)号：US20110040911A1
公开(公告)日：2011-02-17
申请号：US12540545
申请日：2009-08-13
CPC分类号： G06F12/0835
摘要： A dual interface coherent and non-coherent network interface controller architecture is generally presented. In this regard, a network interface controller is introduced including a non-coherent bus interface to communicatively couple with devices of a system through a non-coherent protocol, the non-coherent bus interface to facilitate discovery of the network interface controller by an operating system, a coherent bus interface to communicatively couple with devices of the system through a coherent protocol, and a coherency engine to perform coherent transactions over the coherent interface including to snoop for writes on system memory. Other embodiments are also disclosed and claimed.
摘要翻译： 通常介绍双界面相干和非相干网络接口控制器架构。 在这方面，引入了包括非相干总线接口的网络接口控制器，以通过非相干协议与系统的设备通信耦合，非相干总线接口，以便于操作系统发现网络接口控制器 通过相干协议与系统的设备通信耦合的相干总线接口，以及一致性引擎，用于在相干接口上执行相干事务，包括窥探系统内存上的写入。 还公开并要求保护其他实施例。
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公开(公告)号：US20070002853A1
公开(公告)日：2007-01-04
申请号：US11171597
申请日：2005-06-30
申请人： Anil Vasudevan , D. Bell , Sujoy Sen , Parthasarathy Sarangam
发明人： Anil Vasudevan , D. Bell , Sujoy Sen , Parthasarathy Sarangam
IPC分类号： H04L12/56
CPC分类号： H04L49/355 , H04L49/30
摘要： In one embodiment, it may be determined whether a processor is going to access a packet payload that is stored in a source buffer. If the processor is not going to access the packet payload, a data movement module (DMM) may move the packet payload from the source buffer to a destination buffer.
摘要翻译： 在一个实施例中，可以确定处理器是否要访问存储在源缓冲器中的分组有效载荷。 如果处理器不要访问分组有效载荷，则数据移动模块（DMM）可以将分组有效载荷从源缓冲器移动到目的地缓冲器。
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6.发明申请Method, system, and program for managing transmit throughput for a network controller 审中-公开用于管理网络控制器的传输吞吐量的方法，系统和程序公开(公告)号：US20060004904A1
公开(公告)日：2006-01-05
申请号：US10882540
申请日：2004-06-30
IPC分类号： G06F15/16
CPC分类号： H04L69/161 , H04L69/12 , H04L69/16
摘要： Provided are a method, system, and program for managing transmit throughput for a network controller. In one embodiment, transmit requests from an application may be posted by the device driver to the network controller of the network adapter in a pipeline of transmit requests without waiting for an acknowledgment of the transfer of the accompanying transmit data to the network controller. In another aspect, a device driver monitors the available buffer space of a network controller buffer to ensure that the network controller has sufficient available buffer space before posting the next transmit request to the network controller. In accordance with yet another aspect, the device driver can copy transmit data from an application buffer to a driver buffer if the size of the transmit data of a particular transmit request is below a programmable threshold. If so, the device driver can notify the application to permit the application buffer to be released.
摘要翻译： 提供了一种用于管理网络控制器的发送吞吐量的方法，系统和程序。 在一个实施例中，来自应用的发送请求可以由设备驱动程序以发送请求的流水线发布到网络适配器的网络控制器，而不必等待对所述网络控制器的所附送的传输数据的传送的确认。 在另一方面，设备驱动程序监视网络控制器缓冲器的可用缓冲区空间，以确保网络控制器在向网络控制器发布下一个发送请求之前具有足够的可用缓冲区空间。 根据另一方面，如果特定发送请求的发送数据的大小低于可编程阈值，则设备驱动程序可以将发送数据从应用缓冲器复制到驱动器缓冲器。 如果是这样，设备驱动程序可以通知应用程序以允许释放应用程序缓冲区。
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公开(公告)号：US20130268619A1
公开(公告)日：2013-10-10
申请号：US13995231
申请日：2011-12-01
IPC分类号： H04L12/24
CPC分类号： H04L41/04 , G06F13/385
摘要： An embodiment may include at least one server processor that may control, at least in part, server switch circuitry data and control plane processing. The at least one processor may include at least one cache memory that is capable of being involved in at least one data transfer that involves at least one component of the server. The at least one data transfer may be carried out in a manner that by-passes involvement of server system memory. The switch circuitry may be communicatively coupled to the at least one processor and to at least one node via communication links. The at least one processor may select, at least in part, at least one communication protocol to be used by the links. The switch circuitry may forward, at least in part, via at least one of the links at least one received packet. Many modifications are possible.
摘要翻译： 一个实施例可以包括至少一个可以至少部分地控制服务器交换机电路数据和控制平面处理的服务器处理器。 所述至少一个处理器可以包括至少一个高速缓存存储器，其能够涉及涉及服务器的至少一个组件的至少一个数据传输。 所述至少一个数据传送可以以服务器系统存储器的旁路方式进行。 开关电路可以经由通信链路通信地耦合到至少一个处理器和至少一个节点。 至少一个处理器可以至少部分地选择要由链路使用的至少一个通信协议。 交换机电路可以至少部分地经由至少一个链路至少一个接收的分组转发。 许多修改是可能的。
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公开(公告)号：US07987307B2
公开(公告)日：2011-07-26
申请号：US11525738
申请日：2006-09-22
CPC分类号： G06F13/26
摘要： In an embodiment, a method is provided. The method of this embodiment provides determining a flow context associated with a receive packet; and if the flow context complies with a dynamic interrupt moderation policy having one or more rules, generating an interrupt to process the receive packet substantially independently of an interrupt generated in accordance with an interrupt coalescing scheme (“coalesced interrupt”). Other embodiments are disclosed and/or claimed.
摘要翻译： 在一个实施例中，提供了一种方法。 该实施例的方法提供确定与接收分组相关联的流上下文; 并且如果流上下文符合具有一个或多个规则的动态中断调节策略，则生成中断以基本上独立于根据中断聚合方案（“合并中断”）生成的中断来处理接收分组。 披露和/或要求保护的其它实施例。
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公开(公告)号：US09009367B2
公开(公告)日：2015-04-14
申请号：US13566298
申请日：2012-08-03
CPC分类号： G06F13/24 , H04L69/165
摘要： Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.
摘要翻译： 通常，本公开涉及自适应中断调节。 方法可以包括：至少部分地基于与每个连接相关联的连接标识符，由主机设备确定主机设备与一个或多个链路伙伴之间的连接数; 由所述主机设备至少部分地基于多个连接来确定新的中断率; 通过所述主机设备更新具有与所述新中断速率相关的值的中断调节定时器; 并配置中断调节定时器以允许以新的中断速率发生中断。
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公开(公告)号：US20200183732A1
公开(公告)日：2020-06-11
申请号：US16710556
申请日：2019-12-11
摘要： Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located. After asserting an interrupt, an RX queue may be auto-masked to prevent generation of additional events when new descriptors are enqueued in the RX queue.
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