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公开(公告)号：US08558597B2
公开(公告)日：2013-10-15
申请号：US13538621
申请日：2012-06-29
IPC分类号： H03H11/16
CPC分类号： H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
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公开(公告)号：US20130207708A1
公开(公告)日：2013-08-15
申请号：US13538621
申请日：2012-06-29
IPC分类号： H03K5/13
CPC分类号： H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
摘要翻译： 提供了相位插值器电路，其通过在第一和第二时钟信号的相位之间进行内插来产生输出时钟信号。 通过检测第一时钟信号的边沿并施加第一电流来将输出节点的电容充电至小于或等于电压比较器的切换阈值的电压电平，并且检测第 第二时钟信号，并且施加第二电流以将输出节点的电容充电到超过电压比较器的切换阈值的电压电平。 改变第一电流的大小以调节输出节点的电容被充电到超过电压比较器的切换阈值的电压电平的时刻，并调整从电压比较器输出的输出时钟信号的相位 。
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公开(公告)号：US20130207707A1
公开(公告)日：2013-08-15
申请号：US13538276
申请日：2012-06-29
IPC分类号： H03K5/13
CPC分类号： H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
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公开(公告)号：US08564352B2
公开(公告)日：2013-10-22
申请号：US13538276
申请日：2012-06-29
IPC分类号： H03H11/16
CPC分类号： H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
摘要翻译： 提供了相位插值器电路，其通过在第一和第二时钟信号的相位之间进行内插来产生输出时钟信号。 通过检测第一时钟信号的边沿并施加第一电流来将输出节点的电容充电至小于或等于电压比较器的切换阈值的电压电平，并且检测第 第二时钟信号，并且施加第二电流以将输出节点的电容充电到超过电压比较器的切换阈值的电压电平。 改变第一电流的大小以调节输出节点的电容被充电到超过电压比较器的切换阈值的电压电平的时刻，并调整从电压比较器输出的输出时钟信号的相位 。
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公开(公告)号：US08633764B2
公开(公告)日：2014-01-21
申请号：US13157957
申请日：2011-06-10
IPC分类号： H03F3/00
CPC分类号： H03F3/211 , H03F3/45183 , H03F3/45197 , H03F3/45632 , H03F2200/264 , H03F2203/45681
摘要： An apparatus comprises an amplifier circuit comprising at least one output node and a common-mode restoration circuit capacitively coupled to the at least one output node of the amplifier circuit. The common-mode restoration circuit is configured to introduce at least one common-mode restoring signal onto the output node, wherein the at least one common-mode restoring signal transitions in correspondence with an operation interval of the amplifier circuit and thereby compensates for a common-mode voltage drop on the at least one output node of the amplifier circuit. In one example, the amplifier circuit may comprise a current-integrating amplifier circuit, and the operation interval may comprise an integration interval.
摘要翻译： 一种装置包括放大器电路，其包括至少一个输出节点和电容耦合到放大器电路的至少一个输出节点的共模恢复电路。 共模恢复电路被配置为将至少一个共模恢复信号引入到输出节点上，其中至少一个共模恢复信号与放大器电路的操作间隔对应地转变，从而补偿公共 - 放大器电路的至少一个输出节点上的模式电压降。 在一个示例中，放大器电路可以包括电流积分放大器电路，并且操作间隔可以包括积分间隔。
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公开(公告)号：US20130207702A1
公开(公告)日：2013-08-15
申请号：US13534241
申请日：2012-06-27
IPC分类号： H03K3/84
CPC分类号： H03K17/005 , H03K3/017 , H03K5/1565
摘要： Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.
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公开(公告)号：US20130207703A1
公开(公告)日：2013-08-15
申请号：US13534596
申请日：2012-06-27
IPC分类号： H03K3/84
CPC分类号： H03K17/005 , H03K3/017 , H03K5/1565
摘要： Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.
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公开(公告)号：US20120313703A1
公开(公告)日：2012-12-13
申请号：US13157957
申请日：2011-06-10
IPC分类号： H03F3/45
CPC分类号： H03F3/211 , H03F3/45183 , H03F3/45197 , H03F3/45632 , H03F2200/264 , H03F2203/45681
摘要： An apparatus comprises an amplifier circuit comprising at least one output node and a common-mode restoration circuit capacitively coupled to the at least one output node of the amplifier circuit. The common-mode restoration circuit is configured to introduce at least one common-mode restoring signal onto the output node, wherein the at least one common-mode restoring signal transitions in correspondence with an operation interval of the amplifier circuit and thereby compensates for a common-mode voltage drop on the at least one output node of the amplifier circuit. In one example, the amplifier circuit may comprise a current-integrating amplifier circuit, and the operation interval may comprise an integration interval.
摘要翻译： 一种装置包括放大器电路，其包括至少一个输出节点和电容耦合到放大器电路的至少一个输出节点的共模恢复电路。 共模恢复电路被配置为将至少一个共模恢复信号引入到输出节点上，其中至少一个共模恢复信号与放大器电路的操作间隔对应地转变，从而补偿公共 - 放大器电路的至少一个输出节点上的模式电压降。 在一个示例中，放大器电路可以包括电流积分放大器电路，并且操作间隔可以包括积分间隔。
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公开(公告)号：US20190139448A1
公开(公告)日：2019-05-09
申请号：US16235448
申请日：2018-12-28
申请人： Carl S. Marshall , Giuseppe Raffa , Shi Meng , Lama Nachman , Ankur Agrawal , Selvakumar Panneer , Glen J. Anderson , Lenitra M. Durham
发明人： Carl S. Marshall , Giuseppe Raffa , Shi Meng , Lama Nachman , Ankur Agrawal , Selvakumar Panneer , Glen J. Anderson , Lenitra M. Durham
IPC分类号： G09B19/06 , G06F17/27 , G06K9/00 , G06F16/907 , G09B7/02
摘要： Language education systems capable of integrating with a user's daily life and automatically producing educational prompts would be particularly advantageous. An example method includes determining a user's identity, detecting a language education subject, prompting the user with a language education message, receiving a user's response, and updating a user profile associated with the user based on the user's response. Methods may also include determining user state (including emotional, physical, social, etc.) and determining, based on the user state, whether to prompt the user with the language education prompt.
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公开(公告)号：US08484417B2
公开(公告)日：2013-07-09
申请号：US13337093
申请日：2011-12-24
申请人： Lu Xun , Hua-Jun Zeng , Muralidhar Krishnaprasad , Radhakrishnan Srikanth , Ankur Agrawal , Balachandar Pavadaisamy
发明人： Lu Xun , Hua-Jun Zeng , Muralidhar Krishnaprasad , Radhakrishnan Srikanth , Ankur Agrawal , Balachandar Pavadaisamy
CPC分类号： G06F17/30949 , G06F12/0813
摘要： Version indicators within an existing range can be associated with a data partition in a distributed data store. A partition reconfiguration can be associated with one of multiple partitions in the data store, and a new version indicator that is outside the existing range can be assigned to the reconfigured partition. Additionally, a broadcast message can be sent to multiple nodes, which can include storage nodes and/or client nodes that are configured to communicate with storage nodes to access data in a distributed data store. The broadcast message can include updated location information for data in the data store. In addition, a response message can be sent to a requesting node of the multiple nodes in response to receiving from that node a message that requests updated location information for the data. The response message can include the requested updated location information.
摘要翻译： 现有范围内的版本指示器可以与分布式数据存储中的数据分区关联。 分区重新配置可以与数据存储中的多个分区中的一个相关联，并且可以将配置在现有范围之外的新版本指示符分配给重新配置的分区。 另外，广播消息可以被发送到多个节点，其可以包括被配置为与存储节点进行通信以访问分布式数据存储中的数据的存储节点和/或客户端节点。 广播消息可以包括用于数据存储中的数据的更新的位置信息。 此外，响应于从该节点接收到请求数据的更新的位置信息的消息，响应消息可被发送到多个节点的请求节点。 响应消息可以包括所请求的更新位置信息。
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