公开(公告)号：US08564352B2

公开(公告)日：2013-10-22

申请号：US13538276

申请日：2012-06-29

申请人： Ankur Agrawal ,  John F. Bulzacchelli ,  Sergey V. Rylov

发明人： Ankur Agrawal ,  John F. Bulzacchelli ,  Sergey V. Rylov

IPC分类号： H03H11/16

CPC分类号： H04L25/03878 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00065 ,  H04L27/01

摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

摘要翻译： 提供了相位插值器电路，其通过在第一和第二时钟信号的相位之间进行内插来产生输出时钟信号。 通过检测第一时钟信号的边沿并施加第一电流来将输出节点的电容充电至小于或等于电压比较器的切换阈值的电压电平，并且检测第 第二时钟信号，并且施加第二电流以将输出节点的电容充电到超过电压比较器的切换阈值的电压电平。 改变第一电流的大小以调节输出节点的电容被充电到超过电压比较器的切换阈值的电压电平的时刻，并调整从电压比较器输出的输出时钟信号的相位 。

公开(公告)号：US08558597B2

公开(公告)日：2013-10-15

申请号：US13538621

申请日：2012-06-29

申请人： Ankur Agrawal ,  John F. Bulzacchelli ,  Sergey V. Rylov

发明人： Ankur Agrawal ,  John F. Bulzacchelli ,  Sergey V. Rylov

IPC分类号： H03H11/16

CPC分类号： H04L25/03878 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00065 ,  H04L27/01

摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

公开(公告)号：US20130207708A1

公开(公告)日：2013-08-15

申请号：US13538621

申请日：2012-06-29

申请人： Ankur Agrawal ,  John F. Bulzacchelli ,  Sergey V. Rylov

发明人： Ankur Agrawal ,  John F. Bulzacchelli ,  Sergey V. Rylov

IPC分类号： H03K5/13

CPC分类号： H04L25/03878 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00065 ,  H04L27/01

摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

摘要翻译： 提供了相位插值器电路，其通过在第一和第二时钟信号的相位之间进行内插来产生输出时钟信号。 通过检测第一时钟信号的边沿并施加第一电流来将输出节点的电容充电至小于或等于电压比较器的切换阈值的电压电平，并且检测第 第二时钟信号，并且施加第二电流以将输出节点的电容充电到超过电压比较器的切换阈值的电压电平。 改变第一电流的大小以调节输出节点的电容被充电到超过电压比较器的切换阈值的电压电平的时刻，并调整从电压比较器输出的输出时钟信号的相位 。

公开(公告)号：US20130207707A1

公开(公告)日：2013-08-15

申请号：US13538276

申请日：2012-06-29

申请人： Ankur Agrawal ,  John F. Bulzacchelli ,  Sergey V. Rylov

发明人： Ankur Agrawal ,  John F. Bulzacchelli ,  Sergey V. Rylov

IPC分类号： H03K5/13

CPC分类号： H04L25/03878 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00065 ,  H04L27/01

摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

公开(公告)号：US08774228B2

公开(公告)日：2014-07-08

申请号：US13157968

申请日：2011-06-10

申请人： John F. Bulzacchelli ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Yong Liu ,  Sergey V. Rylov

发明人： John F. Bulzacchelli ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Yong Liu ,  Sergey V. Rylov

IPC分类号： H04J3/06

CPC分类号： H04L7/10 ,  H04L7/0337

摘要： Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.

摘要翻译： 提供了用于具有链路冗余的输入/输出总线的定时恢复的方法和装置。 并行输入/输出接口接收器包括多个数据接收器，每个数据接收器被配置为分别从n + m个通道中的相应一个通道接收输入数据，其中n是大于1的整数，并且m是大于或等于1的整数 。 输入数据是n个通道的非校准数据，是m个通道的校准数据。 接口接收器还包括第一相位调节器，其被配置为向多个数据接收器提供第一时钟信号，用于在任何给定时间仅对非校准数据进行采样，以及第二相位调整器，被配置为向第 多个数据接收器，用于在任何给定时间仅对校准数据进行采样。

公开(公告)号：US07893861B2

公开(公告)日：2011-02-22

申请号：US12494496

申请日：2009-06-30

申请人： John F. Bulzacchelli ,  Daniel J. Friedman ,  Shahrzad Naraghi ,  Sergey V. Rylov ,  Alexander V. Rylyakov ,  Zeynep Toprak-Deniz

发明人： John F. Bulzacchelli ,  Daniel J. Friedman ,  Shahrzad Naraghi ,  Sergey V. Rylov ,  Alexander V. Rylyakov ,  Zeynep Toprak-Deniz

IPC分类号： H03M1/50

CPC分类号： H03M1/20 ,  H03M1/1215 ,  H03M1/502

摘要： Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.

摘要翻译： 提供了关于基于时间到数字的模数转换器的装置和方法。 一种装置包括：基于时间 - 数字转换器的模数转换器，用于产生第一信号;以及第二信号，其具有基于采样的第一信号的上升沿和第二信号的上升沿之间的定时关系 输入模拟电压电平，并将定时关系转换成相应的时间 - 数字表示。 在没有任何电压比较和电流比较的情况下获得时间到数字表示。

公开(公告)号：US08704583B2

公开(公告)日：2014-04-22

申请号：US13399054

申请日：2012-02-17

申请人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

发明人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

IPC分类号： H03L5/00 ,  H03F3/45

CPC分类号： H03F1/0261 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/45632 ,  H03F2200/27 ,  H03F2203/45631 ,  H03K19/018528

摘要： Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.

摘要翻译： 提供电容电平移位电路和方法用于将直流偏移添加到电流积分放大器的输出。 例如，电流积分放大器包括输入放大器级和输出偏移电路。 输入放大器级包括输入节点，第一输出节点和连接在第一输出节点和电源节点之间的第一开关。 输出偏移电路连接到输入放大器级的第一输出节点和电流积分放大器的第二输出节点。 输出偏移电路包括耦合在输入放大器级的第一输出节点和电流积分放大器的第二输出节点之间的第一串联电容器。 输出偏移电路将偏置电压切换到第二输出节点并对第一串联电容器充电，以向电流积分放大器的第二输出节点添加DC偏移。

公开(公告)号：US20130214865A1

公开(公告)日：2013-08-22

申请号：US13399054

申请日：2012-02-17

申请人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

发明人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

IPC分类号： H03F3/45

CPC分类号： H03F1/0261 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/45632 ,  H03F2200/27 ,  H03F2203/45631 ,  H03K19/018528

摘要： Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.

摘要翻译： 提供电容电平移位电路和方法用于将直流偏移添加到电流积分放大器的输出。 例如，电流积分放大器包括输入放大器级和输出偏移电路。 输入放大器级包括输入节点，第一输出节点和连接在第一输出节点和电源节点之间的第一开关。 输出偏移电路连接到输入放大器级的第一输出节点和电流积分放大器的第二输出节点。 输出偏移电路包括耦合在输入放大器级的第一输出节点和电流积分放大器的第二输出节点之间的第一串联电容器。 输出偏移电路将偏置电压切换到第二输出节点并对第一串联电容器充电，以向电流积分放大器的第二输出节点添加DC偏移。

公开(公告)号：US20120314721A1

公开(公告)日：2012-12-13

申请号：US13157968

申请日：2011-06-10

申请人： JOHN F. BULZACCHELLI ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Yong Liu ,  Sergey V. Rylov

发明人： JOHN F. BULZACCHELLI ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Yong Liu ,  Sergey V. Rylov

IPC分类号： H04L7/00 ,  H04J3/06

CPC分类号： H04L7/10 ,  H04L7/0337

摘要： Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.

摘要翻译： 提供了用于具有链路冗余的输入/输出总线的定时恢复的方法和装置。 并行输入/输出接口接收器包括多个数据接收器，每个数据接收器被配置为分别从n + m个通道中的相应一个通道接收输入数据，其中n是大于1的整数，并且m是大于或等于1的整数 。 输入数据是n个通道的非校准数据，是m个通道的校准数据。 接口接收器还包括第一相位调节器，其被配置为向多个数据接收器提供第一时钟信号，用于在任何给定时间仅对非校准数据进行采样，以及第二相位调整器，被配置为向第 多个数据接收器，用于在任何给定时间仅对校准数据进行采样。

公开(公告)号：US20100328130A1

公开(公告)日：2010-12-30

申请号：US12494496

申请日：2009-06-30

申请人： John F. Bulzacchelli ,  Daniel J. Friedman ,  Shahrzad Naraghi ,  Sergey V. Rylov ,  Alexander V. Rylyakov ,  Zeynep Toprak-Deniz

发明人： John F. Bulzacchelli ,  Daniel J. Friedman ,  Shahrzad Naraghi ,  Sergey V. Rylov ,  Alexander V. Rylyakov ,  Zeynep Toprak-Deniz

IPC分类号： H03M1/50

CPC分类号： H03M1/20 ,  H03M1/1215 ,  H03M1/502

摘要： Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.

摘要翻译： 提供了关于基于时间到数字的模数转换器的装置和方法。 一种装置包括：基于时间 - 数字转换器的模数转换器，用于产生第一信号;以及第二信号，其具有基于采样的第一信号的上升沿和第二信号的上升沿之间的定时关系 输入模拟电压电平，并将定时关系转换成相应的时间 - 数字表示。 在没有任何电压比较和电流比较的情况下获得时间到数字表示。