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公开(公告)号：US20120313703A1
公开(公告)日：2012-12-13
申请号：US13157957
申请日：2011-06-10
IPC分类号： H03F3/45
CPC分类号： H03F3/211 , H03F3/45183 , H03F3/45197 , H03F3/45632 , H03F2200/264 , H03F2203/45681
摘要： An apparatus comprises an amplifier circuit comprising at least one output node and a common-mode restoration circuit capacitively coupled to the at least one output node of the amplifier circuit. The common-mode restoration circuit is configured to introduce at least one common-mode restoring signal onto the output node, wherein the at least one common-mode restoring signal transitions in correspondence with an operation interval of the amplifier circuit and thereby compensates for a common-mode voltage drop on the at least one output node of the amplifier circuit. In one example, the amplifier circuit may comprise a current-integrating amplifier circuit, and the operation interval may comprise an integration interval.
摘要翻译： 一种装置包括放大器电路，其包括至少一个输出节点和电容耦合到放大器电路的至少一个输出节点的共模恢复电路。 共模恢复电路被配置为将至少一个共模恢复信号引入到输出节点上，其中至少一个共模恢复信号与放大器电路的操作间隔对应地转变，从而补偿公共 - 放大器电路的至少一个输出节点上的模式电压降。 在一个示例中，放大器电路可以包括电流积分放大器电路，并且操作间隔可以包括积分间隔。
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公开(公告)号：US08633764B2
公开(公告)日：2014-01-21
申请号：US13157957
申请日：2011-06-10
IPC分类号： H03F3/00
CPC分类号： H03F3/211 , H03F3/45183 , H03F3/45197 , H03F3/45632 , H03F2200/264 , H03F2203/45681
摘要： An apparatus comprises an amplifier circuit comprising at least one output node and a common-mode restoration circuit capacitively coupled to the at least one output node of the amplifier circuit. The common-mode restoration circuit is configured to introduce at least one common-mode restoring signal onto the output node, wherein the at least one common-mode restoring signal transitions in correspondence with an operation interval of the amplifier circuit and thereby compensates for a common-mode voltage drop on the at least one output node of the amplifier circuit. In one example, the amplifier circuit may comprise a current-integrating amplifier circuit, and the operation interval may comprise an integration interval.
摘要翻译： 一种装置包括放大器电路，其包括至少一个输出节点和电容耦合到放大器电路的至少一个输出节点的共模恢复电路。 共模恢复电路被配置为将至少一个共模恢复信号引入到输出节点上，其中至少一个共模恢复信号与放大器电路的操作间隔对应地转变，从而补偿公共 - 放大器电路的至少一个输出节点上的模式电压降。 在一个示例中，放大器电路可以包括电流积分放大器电路，并且操作间隔可以包括积分间隔。
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公开(公告)号：US20130200934A1
公开(公告)日：2013-08-08
申请号：US13367777
申请日：2012-02-07
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.
摘要翻译： 占空比调整电路包括时钟信号输入节点; 时钟信号输出节点; 耦合到所述时钟信号输入节点的控制电压产生电路; 以及第一反相器，被配置为接收包括在时钟信号输入节点处接收的输入时钟信号和从控制电压产生电路接收的控制电压之和的反相器输入信号，并且在时钟信号输出端输出输出时钟信号 节点，其中所述控制电压的变化被配置为改变所述输出时钟信号的占空比。
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公开(公告)号：US20120133541A1
公开(公告)日：2012-05-31
申请号：US13306650
申请日：2011-11-29
IPC分类号： H03M1/12
摘要： An analog-digital converter includes converter units and a control unit. The converter units each including a comparator for performing a comparison using an input voltage, one or more capacitor ladders each having a signal line connected with first terminals of capacitors and with one input of the comparator, and switches each of which is associated with one of the capacitors, connected to a second terminal of the respective capacitor with a first or a second reference potential, the input voltage being shifted when switching one or more of the switches. The control unit controls the number of converter units, and to set the switching states of the plurality of switches in conversion cycles and to obtain comparison results from each of the comparators in a comparison subsequent to each setting of the switching states.
摘要翻译： 模拟数字转换器包括转换器单元和控制单元。 每个转换器单元包括用于使用输入电压进行比较的比较器，每个具有与电容器的第一端子连接的信号线和比较器的一个输入端的一个或多个电容器梯形，以及每个电容器梯级与 电容器，连接到具有第一或第二参考电位的相应电容器的第二端子，当切换一个或多个开关时，输入电压被移位。 控制单元控制转换器单元的数量，并且在转换周期的每个设置之后的比较中，将转换周期中的多个开关的开关状态设置为每个比较器的比较结果。
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公开(公告)号：US20090060091A1
公开(公告)日：2009-03-05
申请号：US11848599
申请日：2007-08-31
IPC分类号： H04L27/00
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/091 , H03L7/10 , H04L7/0008
摘要： A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.
摘要翻译： 高速接收机包括多个接收机组件。 每个接收器组件包括用于接收数据的采样锁存器，用于控制由采样锁存器采样数据的定时的相位旋转器以及用于提供时钟和数据恢复的时钟跟踪逻辑级。 时钟跟踪逻辑级分为高速早/晚（E / L）逻辑和聚合计数器部分以及由同步逻辑块分隔的低速逻辑部分。 接收机还包括用于接收对应于接收数据的数据速率的输入时钟信号的延迟锁定环路（DLL），提供时钟信号的粗略的延迟调整，并将对应于经调整的时钟信号的多个时钟相位矢量输出到相位 每个接收器组件上的旋转器。 相位旋转器基于从DLL接收的时钟相位矢量来控制数据的采样。 单个稳压电源调节器调节提供给DLL和相位旋转器的电源。
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6.发明申请Clock and Data Recovery System and Method for Clock and Data Recovery Based on a Forward Error Correction 有权基于前向纠错的时钟和数据恢复系统及时钟和数据恢复方法公开(公告)号：US20080209296A1
公开(公告)日：2008-08-28
申请号：US12116151
申请日：2008-05-06
IPC分类号： G06F11/14
CPC分类号： H03M13/336 , H03L7/091 , H04L1/0053 , H04L1/0061 , H04L7/033 , H04L7/048
摘要： The forward error correction based clock and data recovery system includes a data latch for intermediately storing received data, which is triggered by a sampling clock. The system further includes an error determination unit for determining whether which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal. Furthermore, the system includes a clock generator for generating the sampling clock depending on the correction signal.
摘要翻译： 基于前向纠错的时钟和数据恢复系统包括用于中间存储由采样时钟触发的接收数据的数据锁存器。 该系统还包括一个错误确定单元，用于确定哪个采样的接收数据是错误的，并且用于产生一个相位/频率校正信号。 此外，该系统包括用于根据校正信号产生采样时钟的时钟发生器。
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公开(公告)号：US20080137790A1
公开(公告)日：2008-06-12
申请号：US11608962
申请日：2006-12-11
IPC分类号： H04L7/00
CPC分类号： H04L7/0004 , H04L7/0334
摘要： A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the DRR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.
摘要翻译： 公开了一种双模式时钟和数据恢复（CDR）系统。 快速锁定，过采样CDR采集模块可以开始该过程，以在启动数据采集条件下快速创建数据采集时钟信号。 当从输入数据流中提取至少一些数据时，DRR系统可以指示这种稳定性，并切换到接受来自低功率CDR维护模块的控制。 低功率CDR维护模块可以微调并保持数据采集信号的定时。 如果CDR维护模块控制下的数据锁定质量下降到足够的程度，高功率CDR采集模块可以重新启用并重新从低功率模块重新进行控制，直到锁定质量再次足够 要使用的低功耗模块。
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公开(公告)号：US20080111633A1
公开(公告)日：2008-05-15
申请号：US11558127
申请日：2006-11-09
IPC分类号： H03L7/089
CPC分类号： H03L7/107 , H03L7/0898 , H03L7/095 , H03L7/1072 , H03L7/23
摘要： A multi-Gigahertz, low jitter phase locked loop (PLL) with adjustable gain is disclosed. In one embodiment, properties of a fVCO signal of a PLL can be acquired. Properties can include the occurrences of different types of jitter on the fVCO signal and the lock status of the PLL. A gain control module can control at least a portion of the PLL based on an analysis of the acquired properties. For example, when the loop is locked or when there is loop filter leakage, the gain of a charge pump in the PLL can be reduced. When a charge pump mismatch is detected based on the acquired properties, additional control signals can be provided to the charge pump to correct the mismatch.
摘要翻译： 公开了一种具有可调增益的多吉赫兹低抖动锁相环（PLL）。 在一个实施例中，可以获取PLL的f VCO信号的特性。 属性可以包括在VCO上的不同类型的抖动的出现以及PLL的锁定状态。 增益控制模块可以基于所获取的属性的分析来控制PLL的至少一部分。 例如，当环路被锁定或者当存在环路滤波器泄漏时，可以减小PLL中的电荷泵的增益。 当基于获取的特性检测到电荷泵不匹配时，可以向电荷泵提供额外的控制信号以校正不匹配。
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公开(公告)号：US20140070864A1
公开(公告)日：2014-03-13
申请号：US13606940
申请日：2012-09-07
IPC分类号： H03H11/26
CPC分类号： H03K19/00361 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096 , H03K2005/00058
摘要： A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate.
摘要翻译： 配置为控制驱动器电路的转换速率的转换速率控制电路包括：时钟延迟模块，其接收半速率时钟信号，并且包括多个延迟单元，所述多个延迟单元被配置为产生多个相应的延迟时钟信号，每个延迟单元具有不同的时间 相互延迟 驱动器模块包括与相应数据单元电通信的多个多路复用器，以接收对应的延迟时钟信号。 复用器被配置为响应于延迟的时钟信号输出相应的全速率数据流。 转换驱动器模块还包括与每个多路复用器电通信的输出级电路，以组合每个全速率数据流并产生控制转换速率的最终逐步驱动信号。
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公开(公告)号：US20130322512A1
公开(公告)日：2013-12-05
申请号：US13486644
申请日：2012-06-01
IPC分类号： H03H7/40
CPC分类号： H04L25/03146 , H04L2025/03484
摘要： A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator latches having a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions dn-2 and dn-3; and wherein the 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision dn-1 to output a slice output signal dn.
摘要翻译： 用于接收机的判决反馈均衡器（DFE）片包括多个非投机DFE抽头; 和3个推测性DFE抽头，其中3个推测性DFE抽头包括第一和第二多路复用器级，第一和第二多路复用器级中的每一个包括4个比较器锁存器，4个比较器锁存器中的每一个具有可编程偏移量; 以及多路复用器，其从4个比较器锁存器接收4个比较器锁存器输出并输出多路复用器级输出，其中多路复用器由先前的符号决定dn-2和dn-3控制; 并且其中所述3个推测抽头还包括2：1判决复用器级，其接收所述第一和第二多路复用器级的多路复用器级输出，并由先前的符号判定dn-1控制以输出片输出信号dn。
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