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    Method and apparatus for collecting and providing viewer feedback to a broadcast
    1.
    发明授权
    Method and apparatus for collecting and providing viewer feedback to a broadcast 有权
    用于收集和提供观众对广播的反馈的方法和装置

    公开(公告)号：US06317881B1

    公开(公告)日：2001-11-13

    申请号：US09186302

    申请日：1998-11-04

    申请人： Anthony A. Shah-Nazaroff ,  Jean M. Goldschmidt Iki ,  Kenneth A. Moore ,  David N. Hackson ,  Eric O. Smith

    发明人： Anthony A. Shah-Nazaroff ,  Jean M. Goldschmidt Iki ,  Kenneth A. Moore ,  David N. Hackson ,  Eric O. Smith

    IPC分类号： H04N7173

    CPC分类号： H04N21/4826 ,  H04H60/33 ,  H04H60/46 ,  H04H2201/30 ,  H04N7/17354 ,  H04N21/252 ,  H04N21/25833 ,  H04N21/25883 ,  H04N21/25891 ,  H04N21/42204 ,  H04N21/4532 ,  H04N21/4667 ,  H04N21/4756 ,  H04N21/4758 ,  H04N21/812

    摘要： The present invention provides an improved method and apparatus to collect and provide viewer feedback to broadcasts. According to one aspect of the present invention, a rating is generated for a broadcast by a server system. The rating is based at least in part on viewer feedback to the broadcast, and the rating indicates a likelihood of interest in the broadcast for potential subsequent viewers. Access to the rating is then provided so that predications can be made as to whether or not the broadcast will be of interest to potential subsequent viewers. According to another aspect of the present invention, the rating is provided from the server system to an entertainment system, and the broadcast can be selected for viewing at an entertainment system based on the rating generated by the server system. In one embodiment, the viewer feedback is received at the entertainment system in response to a feedback questionnaire.

    摘要翻译： 本发明提供了一种改进的方法和装置，用于收集和提供观众对广播的反馈。 根据本发明的一个方面，由服务器系统产生用于广播的等级。 该评级至少部分地基于观众对广播的反馈，并且评级表示潜在的后续观看者对广播感兴趣的可能性。 然后提供对评级的访问，以便可以对潜在的后续观看者是否感兴趣地进行预测。 根据本发明的另一方面，从服务器系统向娱乐系统提供评级，并且可以基于由服务器系统生成的评级，在娱乐系统上选择广播以进行观看。 在一个实施例中，响应于反馈问卷，在娱乐系统处接收观众反馈。

    Instruction address stack in the data memory of an instruction-pipelined processor
    9.
    发明授权
    Instruction address stack in the data memory of an instruction-pipelined processor 失效

    公开(公告)号：US4399507A

    公开(公告)日：1983-08-16

    申请号：US280417

    申请日：1981-06-30

    申请人： Michael R. Cosgrove, deceased ,  Alexander H. Frey, Jr. ,  Kenneth A. Moore ,  Abraham Peled ,  Frederic N. Ris ,  William W. Sproul, III

    发明人： Michael R. Cosgrove, deceased ,  Alexander H. Frey, Jr. ,  Kenneth A. Moore ,  Abraham Peled ,  Frederic N. Ris ,  William W. Sproul, III

    IPC分类号： G06F9/38 ,  G06F9/42 ,  G06F9/28

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3889 ,  G06F9/4426

    摘要： An instruction pipeline for a data processor is disclosed, in which instruction execution is carried out in a sequence of phases which include fetching the instruction from an instruction storage, computing a data storage address from the fetched instruction, accessing the data storage at the computed address to obtain a datum operand, and then carrying out the logical or arithmetic operation on the accessed datum in accordance with the fetched instruction. Branch and stack instructions and return instructions are accommodated by providing a return address stack in the data storage, which stores the next instruction store address to be returned to after a return operation has been completed. Since the instruction address stack in the data storage cannot be directly accessed by the instruction fetching stage of the pipeline until several instruction execution phases have transpired, without degrading the performance of the pipeline, a stack register is provided in the instruction fetch stage of the pipeline which contains a duplicate of the instruction store address presently residing at the top of the instruction address stack. Then when a return instruction is encountered in the instruction fetch stage, the address of the next instruction to be returned to in the instruction storage is immediately available without interrupting the flow in the pipeline. A stack pointer in a stage of the pipeline between the instruction fetch stage and the data store access stage, then takes advantage of unused instruction phases in the pipeline, to cause the data store access stage to read the next available instruction store address from the instruction address stack therein and load it into the stack register in preparation for the next return instruction. Thus, the data storage and instruction stacking function can be shared in the same data storage device which is accessed by an intermediate stage in the multiple phase instruction pipeline without degrading the performance of the pipeline.