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    Method and apparatus for generating multiple system memory drive strengths
    2.
    发明授权
    Method and apparatus for generating multiple system memory drive strengths 失效
    用于产生多个系统存储器驱动强度的方法和装置

    公开(公告)号：US07161851B2

    公开(公告)日：2007-01-09

    申请号：US10041948

    申请日：2002-01-07

    申请人： Steven A. Peterson ,  Razi Uddin ,  Vishal Sharma

    发明人： Steven A. Peterson ,  Razi Uddin ,  Vishal Sharma

    IPC分类号： G11C7/00

    CPC分类号： H03K19/018585 ,  G06F13/4072 ,  G11C7/1045 ,  G11C7/20

    摘要： A system and method for generating multiple drive strengths for one or more output signals of a memory controller operable to control a memory subsystem. The system includes a state machine operable to generate an n-bit output representative of a drive strength operable to drive the one or more output signals; and a plurality of adders, each adder having a plurality of n-bit inputs, each input receiving a selective set of bits from the n-bit output of the state machine, the adders generating a plurality of n-bit outputs representative of drive strengths operable to drive the output signals. The method includes generating an n-bit output representative of a drive strength, and adding combinations of two or more selective sets of bits from the n-bit output to generate a plurality of n-bit outputs representative of a plurality of drive strengths that are operable to drive the output signal.

    摘要翻译： 一种用于为可操作以控制存储器子系统的存储器控​​制器的一个或多个输出信号产生多个驱动强度的系统和方法。 该系统包括状态机，可操作以产生代表可操作以驱动一个或多个输出信号的驱动强度的n位输出; 和多个加法器，每个加法器具有多个n位输入，每个输入从状态机的n位输出接收一组选择位，加法器产生代表驱动强度的多个n位输出 可操作地驱动输出信号。 该方法包括产生表示驱动强度的n位输出，以及从n位输出中加入两个或更多个选择性位组合的组合，以产生代表多个驱动强度的多个n位输出 可操作地驱动输出信号。

    Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting
    3.
    发明授权
    Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting 有权
    提供使用数字阻抗代码转换的多个电路补偿的单个参考分量的装置和方法

    公开(公告)号：US06756810B2

    公开(公告)日：2004-06-29

    申请号：US10360268

    申请日：2003-02-06

    申请人： Usman A. Mughal ,  Razi Uddin ,  Chee How Lim ,  Steven A. Peterson

    发明人： Usman A. Mughal ,  Razi Uddin ,  Chee How Lim ,  Steven A. Peterson

    IPC分类号： H03K190185

    CPC分类号： H04L25/0298 ,  H03K19/00384 ,  H04L25/026 ,  H04L25/0272

    摘要： A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.

    摘要翻译： 单个外部阻抗元件用于执行多路电路补偿。 首先基于将由晶体管产生的内部阻抗与外部阻抗元件的阻抗进行匹配来产生参考阻抗代码，然后可以根据需要补偿的各种不同电路的阻抗要求，移动参考阻抗代码以产生新的阻抗代码 。 使用单个外部阻抗元件来补偿多个电路可以降低主板和封装成本。 由于可以使用更简单的补偿电路，所以芯片面积也是保守的。

    Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation
    4.
    发明授权
    Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation 有权
    在主从配置中使用单个参考组件进行多电路补偿的装置和方法

    公开(公告)号：US06717455B2

    公开(公告)日：2004-04-06

    申请号：US10338233

    申请日：2003-01-08

    申请人： Usman A. Mughal ,  Razi Uddin ,  Chee How Lim ,  Songmin Kim ,  Gregory F. Taylor

    发明人： Usman A. Mughal ,  Razi Uddin ,  Chee How Lim ,  Songmin Kim ,  Gregory F. Taylor

    IPC分类号： H03K1714

    CPC分类号： H03K19/00384

    摘要： A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is shifted to generate a slave impedance code. The slave impedance code is provided to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e.g., shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation.

    摘要翻译： 单个外部阻抗元件用于执行多路电路补偿。 首先从主电路产生参考阻抗代码，然后偏移参考阻抗代码以产生从阻抗代码。 从属阻抗码被提供给一个或多个从属电路以激活从属电路中的设备。 耦合到从电路的阻抗发生器件然后一次被激活，直到其产生的阻抗对应于由从电路产生的阻抗。 根据需要补偿的各种不同电路的阻抗要求，参考阻抗代码可以递增或递减（例如移位）以产生对应于不同阻抗值的从属阻抗代码。

    Apparatus and method for dynamic on-die termination in an open-drain bus architecture system
    5.
    发明授权
    Apparatus and method for dynamic on-die termination in an open-drain bus architecture system 有权
    开漏总线架构系统中的动态片上终端的装置和方法

    公开(公告)号：US06411122B1

    公开(公告)日：2002-06-25

    申请号：US09698647

    申请日：2000-10-27

    申请人： Usman A. Mughal ,  Razi Uddin ,  Chee How Lim ,  Songmin Kim ,  Steve Peterson ,  Raghu P. Raman

    发明人： Usman A. Mughal ,  Razi Uddin ,  Chee How Lim ,  Songmin Kim ,  Steve Peterson ,  Raghu P. Raman

    IPC分类号： H03K1716

    CPC分类号： H04L25/0278

    摘要： In a system, such as an open-drain bus architecture system, a termination impedance can be dynamically coupled or de-coupled from a bus. The termination impedance is coupled to the bus by a dynamic control circuit if a signal is being received from the bus or if a binary 1 is driven on the bus. The termination impedance is de-coupled from the bus by the dynamic control circuit if a binary 0 is driven on the bus. Coupling the termination impedance to the bus improves signal quality by providing a matching impedance. De-coupling the termination impedance reduces power dissipation and improves receiver noise margin.

    摘要翻译： 在诸如开漏总线架构系统的系统中，终端阻抗可以从总线动态耦合或去耦合。 如果从总线接收到信号或者如果在总线上驱动二进制1，则终端阻抗由动态控制电路耦合到总线。 如果在总线上驱动二进制0，则动态控制电路将终端阻抗从总线解耦。 将终端阻抗耦合到总线通过提供匹配阻抗来改善信号质量。 解耦端接阻抗可降低功耗并提高接收机噪声容限。