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    Process of making a bipolar transistor with a trench-isolated emitter
    3.
    发明授权
    Process of making a bipolar transistor with a trench-isolated emitter 失效
    制造具有沟槽隔离发射极的双极晶体管的工艺

    公开(公告)号：US5008210A

    公开(公告)日：1991-04-16

    申请号：US510637

    申请日：1990-04-18

    申请人： Shang-yi Chiang ,  Wen-Ling M. Huang ,  Clifford I. Drowley ,  Paul V. Voorde

    发明人： Shang-yi Chiang ,  Wen-Ling M. Huang ,  Clifford I. Drowley ,  Paul V. Voorde

    IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732

    CPC分类号： H01L29/66272 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/732 ,  Y10S148/011

    摘要： This invention pertains to a self-aligned trench-isolated emitter structure and the method for forming same. The emitter structure comprises a portion of a bipolar transistor which exhibits improved function due to the emitter structure. A single layer of conductive material forms both the emitter and base contacts in the transistor structure, which structure has particularly shallow emitter and base junctions (about 0.15 micrometer or less). The self-aligned emitter contact, isolated from the base contact by a dielectric filled trench, permits overall size reduction of the device, whereby junction area and accompanying leakage across junctions is reduced. In addition, when the structure of the bipolar transistor is such that the trench isolates the emitter area from both the base contact and the extrinsic base, it is possible to provide improved base conductivity without generating peripheral transistor effects. The bipoloar transistor can be either N-P-N type or P-N-P type depending on the materials of fabrication, although high speed devices are typically of the N-P-N type. The method includes forming a sidewall spacer (246), creating an etch-masking layer (250), removing the spacer, and etching an isolation trench at the location previously occupied by the spacer.

    摘要翻译： 本发明涉及自对准沟槽隔离发射极结构及其形成方法。 发射极结构包括双极晶体管的一部分，其由于发射极结构而表现出改善的功能。 单层导电材料在晶体管结构中形成发射极和基极触点，该结构具有特别浅的发射极和基极结（约0.15微米或更小）。 通过介质填充的沟槽与基极接触隔离的自对准发射极接触允许器件的整体尺寸减小，从而降低了接合面积和相邻的接合泄漏。 此外，当双极晶体管的结构使得沟槽将发射极区域与基极接触和非本征基极隔离时，可以提供改进的基极导电性而不产生周边晶体管效应。 尽管高速器件通常是N-P-N型，但双酚晶体管可以是N-P-N型或P-N-P型，这取决于制造材料。 该方法包括形成侧壁间隔物（246），产生蚀刻掩模层（250），去除间隔物，以及在先前由间隔物占据的位置处蚀刻隔离沟槽。

    DYNAMIC TACTILE USER INTERFACE
    4.
    发明申请
    DYNAMIC TACTILE USER INTERFACE 审中-公开
    动态触觉用户界面

    公开(公告)号：US20150277563A1

    公开(公告)日：2015-10-01

    申请号：US14229577

    申请日：2014-03-28

    申请人： Wen-Ling M. Huang ,  Giuseppe Raffa ,  Glen J. Anderson

    发明人： Wen-Ling M. Huang ,  Giuseppe Raffa ,  Glen J. Anderson

    IPC分类号： G06F3/01 ,  G06F3/0487

    CPC分类号： G06F3/016 ,  G06F1/1694 ,  G06F3/041 ,  G06F2203/0383

    摘要： Systems and methods may provide for a programmable array of tactile elements in which the active elements may be dynamically altered in time and space and in dependence upon the orientation of the device of which it is a part. That device may be part of a wearable device, such as a hat, smart watch, smart glasses, glove, wristband or other garment.

    摘要翻译： 系统和方法可以提供可触发元件的可编程阵列，其中有源元件可以在时间和空间上动态地改变，并且依赖于其作为其一部分的装置的取向。 该装置可以是可穿戴装置的一部分，例如帽子，智能手表，智能眼镜，手套，腕带或其他服装。

    Method for fabricating a semiconductor on insulator device
    5.
    发明授权
    Method for fabricating a semiconductor on insulator device 失效
    半导体绝缘体器件的制造方法

    公开(公告)号：US5792678A

    公开(公告)日：1998-08-11

    申请号：US642134

    申请日：1996-05-02

    申请人： Juergen A. Foerstner ,  Wen-Ling M. Huang ,  Marco Racanelli

    发明人： Juergen A. Foerstner ,  Wen-Ling M. Huang ,  Marco Racanelli

    IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/8249

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A semiconductor on insulator structure (50) includes a silicon layer (30) formed on an insulating substrate (20). The silicon layer (30) is partitioned into two sections (32, 34) which are electrically isolated from each other. The thickness of the silicon layer (30) in a first section (32) of the silicon layer (30) is adjusted independently from the thickness of the silicon layer (30) in a second section (34) of the silicon layer (30). Independently adjusting the thickness of the silicon layer (30) allows optimizing the performance of semiconductor devices (60, 80) fabricated in the first and second sections (32, 34) of the semiconductor on insulator structure (50).

    摘要翻译： 半导体绝缘体结构（50）包括形成在绝缘基板（20）上的硅层（30）。 硅层（30）被分隔成彼此电绝缘的两个部分（32,34）。 在硅层（30）的第二部分（34）中，与硅层（30）的厚度独立地调节硅层（30）的第一部分（32）中的硅层（30）的厚度， 。 独立地调整硅层（30）的厚度允许优化在半导体绝缘体结构（50）的第一和第二部分（32,34）中制造的半导体器件（60,80）的性能。

    Bipolar transistor with trench-isolated emitter
    7.
    发明授权
    Bipolar transistor with trench-isolated emitter 失效
    具有沟槽隔离发射极的双极晶体管

    公开(公告)号：US5144403A

    公开(公告)日：1992-09-01

    申请号：US595725

    申请日：1990-10-09

    申请人： Shang-yi Chiang ,  Wen-Ling M. Huang ,  Clifford I. Drowley ,  Paul V. Voorde

    发明人： Shang-yi Chiang ,  Wen-Ling M. Huang ,  Clifford I. Drowley ,  Paul V. Voorde

    IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732

    CPC分类号： H01L29/66272 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/732

    摘要： This invention pertains to a self-aligned, trench-isolated emitter structure and the method for forming same. The emitter structure comprises a portion of a bipolar transistor which exhibits improved function due to the emitter structure. A single layer of conductive material forms both the emitter and base contacts in the transistor structure, which structure has particularly shallow emitter and base junctions (about 0.15 micrometer or less). The self-aligned emitter contact, isolated from the base contact by a dielectric filled trench, permits overall size reduction of the device, whereby junction area and accompanying leakage across junctions is reduced. In addition, when the structure of the bipolar transistor is such that the trench isolates the emitter area from both the base contact and the extrinsic base, it is possible to provide improved base conductivity without generating peripheral transistor effects. The bipolar transistor can be either N-P-N type or P-N-P type depending on the materials of fabrication, although high speed devices are typically of the N-P-N type.

    摘要翻译： 本发明涉及自对准，沟槽隔离的发射极结构及其形成方法。 发射极结构包括双极晶体管的一部分，其由于发射极结构而表现出改善的功能。 单层导电材料在晶体管结构中形成发射极和基极触点，该结构具有特别浅的发射极和基极结（约0.15微米或更小）。 通过介质填充的沟槽与基极接触隔离的自对准发射极接触允许器件的整体尺寸减小，从而降低了接合面积和相邻的接合泄漏。 此外，当双极晶体管的结构使得沟槽将发射极区域与基极接触和非本征基极隔离时，可以提供改进的基极导电性而不产生周边晶体管效应。 尽管高速器件通常是N-P-N型，但双极晶体管可以是N-P-N型或P-N-P型，这取决于制造材料。

    Semiconductor-on-insulator transistor having a doping profile for fully-depleted operation
    9.
    发明授权
    Semiconductor-on-insulator transistor having a doping profile for fully-depleted operation 失效
    具有用于完全耗尽操作的掺杂分布的绝缘体上半导体晶体管

    公开(公告)号：US5656844A

    公开(公告)日：1997-08-12

    申请号：US507898

    申请日：1995-07-27

    申请人： Kevin M. Klein ,  Wen-Ling M. Huang ,  Jun Ma

    发明人： Kevin M. Klein ,  Wen-Ling M. Huang ,  Jun Ma

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/01 ,  H01L27/12 ,  H01L29/76

    CPC分类号： H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78657

    摘要： A semiconductor-on-insulator transistor (10) has a channel region (30) in a semiconductor film (16) under a gate insulating layer (26). The channel region has a top dopant concentration N.sub.T at a top surface (32) of the film that is significantly greater than a bottom dopant concentration N.sub.B at a bottom surface (34) of the film. This non-uniform doping profile provides an SOI device that operates in a fully-depleted mode, yet permits thicker films without a significant degradation of sub-threshold slope.

    摘要翻译： 绝缘体上半导体晶体管（10）在栅极绝缘层（26）下方的半导体膜（16）中具有沟道区（30）。 沟道区在薄膜的顶表面（32）处具有明显大于薄膜底表面（34）处的底部掺杂剂浓度NB的顶部掺杂剂浓度NT。 这种非均匀掺杂分布提供了以完全耗尽模式工作的SOI器件，但允许较厚的膜，而不会明显降低子阈值斜率。

    Bipolar transistor containing a self-aligned emitter contact and method for forming transistor
    10.
    发明授权
    Bipolar transistor containing a self-aligned emitter contact and method for forming transistor 失效
    包含自对准发射极接触的双极晶体管和用于形成晶体管的方法

    公开(公告)号：US5121184A

    公开(公告)日：1992-06-09

    申请号：US664685

    申请日：1991-03-05

    申请人： Wen-Ling M. Huang ,  Kristin Brigham

    发明人： Wen-Ling M. Huang ,  Kristin Brigham

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/768 ,  H01L23/532 ,  H01L29/732

    CPC分类号： H01L29/66272 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/53271 ,  H01L29/7322 ,  H01L2924/0002

    摘要： In a process for fabricating a bipolar transistor with a single polysilicon layer, a silicon nitride layer 22 and a phospho-silicate glass layer 24 are formed on top of the polysilicon layer and the link oxide layers. The glass layer 24 has a high etch selectivity compared to the nitride layer 22 so that the glass layer may be overetched above the emitter polysilicon region without overetching the link oxide. The nitride layer is then removed by etching without significantly affecting the link oxide layer. Thus the emitter metal contact may be self-aligned on top of the emitter polysilicon region 14, 114.

    摘要翻译： 在制造具有单个多晶硅层的双极晶体管的工艺中，在多晶硅层和连接氧化物层的顶部上形成氮化硅层22和磷硅酸盐玻璃层24。 与氮化物层22相比，玻璃层24具有高的蚀刻选择性，使得玻璃层可以在发射极多晶硅区域上方过蚀刻，而不会过氧化连接氧化物。 然后通过蚀刻去除氮化物层，而不显着影响环氧化物层。 因此，发射极金属接触可以在发射极多晶硅区域14,114的顶部自对准。