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公开(公告)号：US07318209B2
公开(公告)日：2008-01-08
申请号：US10616881
申请日：2003-07-10
IPC分类号： G06F17/50
CPC分类号： H03K5/1565 , H03L7/06
摘要： A method and an apparatus are provided for limiting a pulse width in a chip clock design of a circuit. The circuit receives a clock signal having a clock pulse width. The clock pulse width of the clock signal is detected. It is determined whether the clock pulse width is larger than a maximum clock pulse width. Upon a determination that the clock pulse width is larger than a maximum clock pulse width, the clock pulse width of the clock signal is limited.
摘要翻译： 提供了一种用于限制电路的芯片时钟设计中的脉冲宽度的方法和装置。 该电路接收具有时钟脉冲宽度的时钟信号。 检测时钟信号的时钟脉冲宽度。 确定时钟脉冲宽度是否大于最大时钟脉冲宽度。 在确定时钟脉冲宽度大于最大时钟脉冲宽度的情况下，时钟信号的时钟脉冲宽度受到限制。
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公开(公告)号：US07913132B2
公开(公告)日：2011-03-22
申请号：US12273985
申请日：2008-11-19
申请人： Tobias Gemmeke , Dieter Wendel , Holger Wetter , Jens Leenstra
发明人： Tobias Gemmeke , Dieter Wendel , Holger Wetter , Jens Leenstra
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.
摘要翻译： 公开了用于扫描顺序逻辑元件的数字系统和方法。 数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。 至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。 可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。
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公开(公告)号：US07650554B2
公开(公告)日：2010-01-19
申请号：US11563702
申请日：2006-11-28
CPC分类号： G01R31/31725 , G01R31/31922
摘要： A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated circuit, generating a test pattern according to a predetermined scheme, and applying the test pattern to the functional unit, comparing a response from the functional unit with an expected test pattern. If the response differs from the expected test pattern, then an internal failure signal is generated and the internal failure signal is extended to a length, which may be recognized by the test system. Further the present invention relates to a high-speed integrated circuit with at least one functional unit and built-in self-test features.
摘要翻译： 一种用于通过低速测试系统执行具有至少一个功能单元的高速集成电路测试和内置自检特征的方法。 该方法包括以下步骤：将来自测试系统的外部时钟信号变换成集成电路内更快的内部时钟信号，根据预定方案生成测试模式，并将测试模式应用于功能单元，比较来自 具有预期测试模式的功能单元。 如果响应与预期测试模式不同，则产生内部故障信号，并将内部故障信号扩展到可被测试系统识别的长度。 此外，本发明涉及具有至少一个功能单元和内置自检特征的高速集成电路。
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公开(公告)号：US07225419B2
公开(公告)日：2007-05-29
申请号：US10962121
申请日：2004-10-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种方法，包括以下步骤：（1）接收具有多个锁存器的电路设计; 以及（2）允许电路设计的一个或多个闩锁在电路设计的定时行为建模期间被局部处理为呈现闩锁透明度。 提供了许多其他方面。
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公开(公告)号：US20050135179A1
公开(公告)日：2005-06-23
申请号：US11010902
申请日：2004-12-13
申请人： Martin Eckert , Juergen Pille , Dieter Wendel
发明人： Martin Eckert , Juergen Pille , Dieter Wendel
CPC分类号： G11C7/1075 , G11C8/16
摘要： A multiport array comprises a read section which is separated from an array of memory cells and which forms a plurality of data-out ports each consisting of a predetermined number of output lines. The read section comprises a multiplex network containing a plurality of multiplex arrays each associated with one of the data-out ports (0,1, . . . ,15). The multiplex arrays are connected to the data read lines of the memory cells and are selected by read addresses. The multiplex arrays comprise transmission elements which connect selected ones of the data read lines to the associated data-out port.
摘要翻译： 多端口阵列包括与存储器单元阵列分离并且形成多个数据输出端口的读取部件，每个数据输出端口由预定数量的输出线路组成。 读取部分包括多路复用网络，该多路复用网络包含多个多路复用阵列，每个多路复用阵列与数据输出端口（0,1，...，15）之一相关联。 多路复用阵列连接到存储单元的数据读取线，并通过读地址进行选择。 多路复用阵列包括将选定数据读取线连接到相关联的数据输出端口的传输元件。
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公开(公告)号：US06219296B1
公开(公告)日：2001-04-17
申请号：US09597954
申请日：2000-06-20
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： A multiport memory cell having a reduced number of write wordlines is disclosed. The multiport memory cell capable of simultaneously reading data from and writing data to a storage cell comprises a storage cell for storing data, a decoder, write wordlines, write bitlines, read wordlines, and read bitlines. The write wordlines and the write bitlines are utilized to input write data into the storage cell. The read wordlines and the read bitlines are utilized to output data from the storage cell. The write bitlines are directly coupled to the storage cell, and some or all of the write wordlines are coupled to the storage cell via the decoder for the purpose of wire reduction. Similar to the write bitlines, all the read bitlines and read wordlines are directly coupled to the storage cell.
摘要翻译： 公开了具有减少数量的写字线的多端口存储单元。 能够同时从存储单元读取数据并将数据写入存储单元的多端口存储单元包括用于存储数据的存储单元，解码器，写字线，写位线，读字线和读位线。 写入字线和写位线用于将写入数据输入存储单元。 读取字线和读位线用于从存储单元输出数据。 写入位线直接耦合到存储单元，并且为了减少线的目的，部分或全部写入字线通过解码器耦合到存储单元。 与写入位线类似，所有读取的位线和读取字线都直接耦合到存储单元。
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7.发明授权Circular buffer with n sequential real and virtual entry positions for selectively inhibiting n adjacent entry positions including the virtual entry positions 失效循环缓冲器，具有n个连续的实际和虚拟进入位置，用于选择性地抑制包括虚拟进入位置在内的n个相邻入口位置
公开(公告)号：US5923900A
公开(公告)日：1999-07-13
申请号：US814511
申请日：1997-03-10
摘要： The invention relates to a circular buffer containing a sequence of entries, and in particular to determining a sequential priority among entries which both fulfill a given condition and are contained in said sequence. This problem is not straightforward, because said sequence of entries may wrap-around in said circular buffer, which means that said sequence of entries extends beyond the last entry position of the buffer. According to the invention, first, a number of virtual entry positions, which is at least equal to the number of real entry positions in the buffer, is added to the non-occupied part of the buffer. In a second step, each entry which fulfills the given condition blocks a certain number of adjacent entries, including said virtual entries. One entry will remain which is not blocked, and which also fulfills the given condition. This entry is the entry with sequential priority.
摘要翻译： 本发明涉及一种包含条目序列的循环缓冲器，特别涉及确定既满足给定条件又包含在所述序列中的条目之间的顺序优先级。 这个问题并不简单，因为所述条目序列可以在所述循环缓冲器中循环，这意味着所述条目序列延伸超过缓冲器的最后入口位置。 根据本发明，首先，至少等于缓冲器中的实际入口位置的数量的虚拟入口位置被添加到缓冲器的非占用部分。 在第二步骤中，满足给定条件的每个条目阻止一定数量的相邻条目，包括所述虚拟条目。 一个条目将保持不被阻止，并且也符合给定条件。 此条目是具有顺序优先级的条目。
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公开(公告)号：US5764587A
公开(公告)日：1998-06-09
申请号：US765987
申请日：1997-01-10
CPC分类号： G11C29/78 , G11C29/848
摘要： The invention relates to a memory device comprising a set of word decoders W, a set of wordline drivers WL, a plurality of switches S to connect a subset of the wordline drivers to the set of word decoders and storage means 5 for the storage of information indicative of a defective wordline. The wordline drivers include a predefined subset of wordline drivers which are to be used when none of the wordlines are defective and a plurality of second subsets of wordline drivers which are to be used when one of the wordlines is defective. The memory device further includes logic means 4 for logically and permanently assigning one of the subsets to the set of word decoders in response to the information stored in the storage means, by controlling the switches S to connect one of the second subsets of wordline drivers to the set of word decoders.
摘要翻译： PCT No.PCT / EP95 / 02183 Sec。 371日期1997年1月10日 102（e）日期1997年1月10日PCT归档1995年6月7日PCT公布。 公开号WO96 / 41264 日期：1996年12月19日本发明涉及包括一组字解码器W，一组字线驱动器WL，多个开关S以将字线驱动器的子集连接到一组字解码器和存储装置5的存储器件 用于存储指示有缺陷的字线的信息。 字线驱动器包括字线驱动器的预定义子集，当字线不是有缺陷时要使用的字线驱动器的子集，以及当字线之一有缺陷时要使用的多个字线驱动器的第二子集。 存储装置还包括逻辑装置4，用于通过控制开关S将字线驱动器的第二子集中的一个连接到字线驱动器的一个，将逻辑上和永久地将一个子集合分配给字解码器集合，以响应存储在存储装置中的信息 一组字解码器。
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公开(公告)号：US5742616A
公开(公告)日：1998-04-21
申请号：US486468
申请日：1995-06-07
申请人： Otto Torreiter , Roland Metzger , Dieter Wendel
发明人： Otto Torreiter , Roland Metzger , Dieter Wendel
IPC分类号： G06F11/10 , G06F12/14 , G06F12/16 , G06F15/78 , G06F21/00 , G06F21/24 , G11C29/40 , G11C29/44 , G01R31/28
CPC分类号： G06F21/79 , G06F12/1466 , G06F21/64 , G11C29/40 , G11C29/44 , G06F11/1004
摘要： A self test circuit provides a general statement about the condition of a coupled memory which indicates whether a wanted or unwanted manipulation or alteration of the memory has occurred. The contents of the memory are not derivable from the general statement. The general statement is preferably a "fail" or "pass" statement stating whether a deviation in the contents of the memory with respect to a last executed test has been detected or not. The testing of a non-volatile memory is executed by generating a signature from the contents of the non-volatile memory and comparing the generated signature with a reference value of the signature. When the comparison of the generated signature with the reference value indicates a different, a signal is issued and access to the non-volatile memory is restricted and/or a failure procedure is started. Access to the non-volatile memory is allowed when the comparison signature with the reference value indicates no difference. In order to allow a test of whether an alteration of the contents of the non-volatile memory has happened between successive authorized applications, a new signature from the contents of the non-volatile memory is generated after each application and stored as a new reference value.
摘要翻译： 自检电路提供关于耦合存储器的状况的一般说明，其指示是否发生了想要的或不需要的操作或改变存储器。 内存的内容不能从一般语句中推导出来。 一般性声明优选地是“失败”或“通过”声明，说明是否已经检测到相对于最后执行的测试的存储器的内容的偏差。 通过从非易失性存储器的内容生成签名并将生成的签名与签名的参考值进行比较来执行非易失性存储器的测试。 当生成的签名与参考值的比较指示不同时，发出信号并且限制访问非易失性存储器和/或启动故障过程。 当与参考值的比较签名没有差异时，允许访问非易失性存储器。 为了允许在连续授权的应用程序之间发生非易失性存储器的内容的改变的测试，在每个应用程序之后生成来自非易失性存储器的内容的新签名，并将其存储为新的参考值 。
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公开(公告)号：US08312069B2
公开(公告)日：2012-11-13
申请号：US11872811
申请日：2007-10-16
申请人： Tobias Gemmeke , Jens Leenstra , Dieter Wendel
发明人： Tobias Gemmeke , Jens Leenstra , Dieter Wendel
IPC分类号： G06F7/00
CPC分类号： G06F13/4217 , Y02D10/14 , Y02D10/151
摘要： A permute unit includes permute logic and a crossbar working in cycles defined by clocking signals and generates one valid output vector per cycle by treating two parallel input vectors per cycle. The permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals. In the first inner cycle, first halves of both input vectors are treated. In the second inner cycle, second halves of both input vectors are treated and a valid output vector is generated from the results of the treatments within the first and the second inner cycles.
摘要翻译： 置换单元包括置换逻辑和交叉开关，其周期由定时信号定义，并且通过每个周期处理两个并行输入向量来产生每个周期的一个有效输出向量。 置换单元通过每个外部周期执行两个内部循环由时钟信号定义来进行双重泵浦。 在第一个内循环中，处理两个输入向量的前半部分。 在第二内循环中，处理两个输入向量的第二半，并且从第一和第二内循环中的处理结果生成有效的输出向量。
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