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    Bulk substrate FET integrated on CMOS SOI
    3.
    发明授权
    Bulk substrate FET integrated on CMOS SOI 有权
    集成在CMOS SOI上的散装衬底FET

    公开(公告)号：US08232599B2

    公开(公告)日：2012-07-31

    申请号：US12683456

    申请日：2010-01-07

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    IPC分类号： H01L27/12 ,  H01L21/86

    CPC分类号： H01L27/1207 ,  H01L21/84

    摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

    摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

    BULK SUBSTRATE FET INTEGRATED ON CMOS SOI
    4.
    发明申请
    BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
    集成在CMOS SOI上的基极FET

    公开(公告)号：US20120187492A1

    公开(公告)日：2012-07-26

    申请号：US13425681

    申请日：2012-03-21

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    IPC分类号： H01L27/088

    CPC分类号： H01L27/1207 ,  H01L21/84

    摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

    摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

    METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES
    5.
    发明申请
    METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES 审中-公开
    用于减少前浇口结构中顶部止点效应的方法

    公开(公告)号：US20080188089A1

    公开(公告)日：2008-08-07

    申请号：US11671668

    申请日：2007-02-06

    申请人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

    发明人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

    IPC分类号： H01L21/31

    CPC分类号： H01L21/32105 ,  H01L21/28035 ,  H01L21/28247

    摘要： A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.

    摘要翻译： 用于减少预掺杂栅极结构中的顶部切口效应的方法包括将经蚀刻的预掺杂栅极堆叠结构进行再氧化处理，所述再氧化工艺包括自由基辅助再氧化工艺，以便导致 在蚀刻的栅堆叠结构的垂直侧壁和水平顶表面上形成氧化物层。 所得到的氧化物层具有与栅极堆叠结构的晶界取向无关的基本均匀的厚度，而与其中存在的掺杂剂材料的浓度和位置无关。

    Gated diode structure for eliminating RIE damage from cap removal
    6.
    发明授权
    Gated diode structure for eliminating RIE damage from cap removal 失效
    门二极管结构，用于消除去除盖子的RIE损坏

    公开(公告)号：US08779551B2

    公开(公告)日：2014-07-15

    申请号：US13489537

    申请日：2012-06-06

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    IPC分类号： H01L27/06

    CPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/77 ,  H01L21/823835 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/861

    摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

    摘要翻译： 一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻 其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。 半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。 优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。 没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

    SOI transistor having a carrier recombination structure in a body
    7.
    发明授权
    SOI transistor having a carrier recombination structure in a body 失效
    在体内具有载流子复合结构的SOI晶体管

    公开(公告)号：US07956415B2

    公开(公告)日：2011-06-07

    申请号：US12133686

    申请日：2008-06-05

    申请人： Anthony I. Chou ,  Andres Bryant ,  Arvind Kumar ,  Shreesh Narasimha

    发明人： Anthony I. Chou ,  Andres Bryant ,  Arvind Kumar ,  Shreesh Narasimha

    IPC分类号： H01L27/12

    CPC分类号： H01L29/66772 ,  H01L29/78603 ,  H01L29/78612

    摘要： A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor.

    摘要翻译： 顶部半导体层形成有两个不同的厚度，使得在顶部半导体层和下面的掩埋绝缘体层之间的界面处在绝缘体上半导体（SOI）场效应晶体管的体区之下形成台阶。 身体区域中的界面和伴随的界面缺陷提供了复合中心，这增加了身体区域中的空穴和电子之间的复合速率。 任选地，包括作为复合中心的材料的间隔物部分形成在台阶的侧壁上，以在体区中的空穴和电子之间提供增强的复合率，这增加了SOI场效应晶体管的双极击穿电压。

    METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE
    8.
    发明申请
    METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE 有权
    具有降低PARASITIC电容的SOI体接触FET的方法和结构

    公开(公告)号：US20090315138A1

    公开(公告)日：2009-12-24

    申请号：US12141276

    申请日：2008-06-18

    申请人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L27/12 ,  H01L21/3205

    CPC分类号： H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.

    摘要翻译： 在一个实施例中，本发明提供一种半导体器件，其包括衬底，该衬底包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。

    GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL
    9.
    发明申请
    GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL 失效
    用于消除从盖拆卸中的RIE损伤的栅极二极管结构

    公开(公告)号：US20130328124A1

    公开(公告)日：2013-12-12

    申请号：US13489537

    申请日：2012-06-06

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    IPC分类号： H01L27/06 ,  H01L21/8238

    CPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/77 ,  H01L21/823835 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/861

    摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

    摘要翻译： 一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻 其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。 半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。 优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。 没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

    BULK SUBSTRATE FET INTEGRATED ON CMOS SOI
    10.
    发明申请
    BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
    集成在CMOS SOI上的基极FET

    公开(公告)号：US20110163383A1

    公开(公告)日：2011-07-07

    申请号：US12683456

    申请日：2010-01-07

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    IPC分类号： H01L27/12 ,  H01L21/86

    CPC分类号： H01L27/1207 ,  H01L21/84

    摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

    摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。