利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.023 秒)

    Gated diode structure for eliminating RIE damage from cap removal
    1.
    发明授权
    Gated diode structure for eliminating RIE damage from cap removal 失效
    门二极管结构，用于消除去除盖子的RIE损坏

    公开(公告)号：US08779551B2

    公开(公告)日：2014-07-15

    申请号：US13489537

    申请日：2012-06-06

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    IPC分类号： H01L27/06

    CPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/77 ,  H01L21/823835 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/861

    摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

    摘要翻译： 一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻 其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。 半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。 优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。 没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

    GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL
    2.
    发明申请
    GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL 失效
    用于消除从盖拆卸中的RIE损伤的栅极二极管结构

    公开(公告)号：US20130328124A1

    公开(公告)日：2013-12-12

    申请号：US13489537

    申请日：2012-06-06

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

    IPC分类号： H01L27/06 ,  H01L21/8238

    CPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/77 ,  H01L21/823835 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/861

    摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

    摘要翻译： 一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻 其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。 半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。 优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。 没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

    Early detection test for identifying defective semiconductor wafers in a front-end manufacturing line
    3.
    发明授权
    Early detection test for identifying defective semiconductor wafers in a front-end manufacturing line 有权
    用于识别前端生产线中有缺陷的半导体晶片的早期检测测试

    公开(公告)号：US07381577B2

    公开(公告)日：2008-06-03

    申请号：US10907870

    申请日：2005-04-19

    申请人： Dustin K. Slisher

    发明人： Dustin K. Slisher

    IPC分类号： G01R31/26

    CPC分类号： H01L22/20

    摘要： A method and apparatus for identifying defective partially manufactured semiconductor wafers in a manufacturing line is described, wherein defects caused by silicon erosion created by over-etching the wafer can be detected. The method described herein is based on an in-line test of selected structures, such as FETs, located in the kerfs that surround the integrated circuit chips. Leakage current between the gate and the source-drain region is measured at FETs in each kerf. Based on the measurement, a leakage current map is created and compared to a standard map. In accordance with this comparison and to the distribution of patterns of leakage currents, it is determined whether or not the wafer is defective. This determination is performed in the kerfs after formation of the gate and source-drain regions, and prior to the wafer being completed. By detecting defective wafers at an early stage, considerable manufacturing resources are saved.

    摘要翻译： 描述了一种用于识别生产线中部分制造的半导体晶圆缺陷的方法和装置，其中可以检测由过度蚀刻晶片而产生的硅腐蚀引起的缺陷。 本文描述的方法基于位于围绕集成电路芯片的切口中的所选结构（例如FET）的在线测试。 在每个切口的FET处测量栅极和源极 - 漏极区域之间的漏电流。 基于测量，创建泄漏电流图并与标准图进行比较。 根据该比较以及泄漏电流图案的分布，确定晶片是否有故障。 在栅极和源极 - 漏极区域形成之后并且在晶片完成之前，在切割中执行该确定。 通过早期检测缺陷晶片，节省了相当多的制造资源。

    Self-protected electrostatic discharge field effect transistor (SPESDFET), an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and associated methods of forming the SPESDFET and the integrated circuit
    7.
    发明授权
    Self-protected electrostatic discharge field effect transistor (SPESDFET), an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and associated methods of forming the SPESDFET and the integrated circuit 有权
    自保护静电放电场效应晶体管（SPESDFET），一种集成了SPESDFET作为输入/输出（I / O）焊盘驱动器的集成电路，以及形成SPESDFET和集成电路的相关方法

    公开(公告)号：US08610217B2

    公开(公告)日：2013-12-17

    申请号：US12967114

    申请日：2010-12-14

    申请人： Robert J. Gauthier, Jr. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

    发明人： Robert J. Gauthier, Jr. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

    IPC分类号： H01L23/62

    CPC分类号： H01L23/60 ,  H01L27/0266 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.

    摘要翻译： 公开了自保护静电放电场效应晶体管（SPESDFET）的实施例。 在SPESDFET实施例中，电阻区域横向定位在深源极/漏极区域的两个离散部分之间：与沟道区域相邻的第一部分和接触的第二部分。 深源极/漏极区域的第二部分被硅化，但是与沟道区域和电阻区域相邻的第一部分是非硅化的。 另外，栅极结构可以是硅化的或非硅化的。 利用这种配置，所公开的SPESDFET提供强大的ESD保护，而不消耗额外的面积，而不改变基本FET设计（例如，不增加深源/漏区和沟道区之间的距离）。 还公开了将SPESDFET作为输入/输出（I / O）焊盘驱动器和用于形成SPESDFET和集成电路的方法实施例的集成电路的实施例。

    TOOL COMMONALITY AND STRATIFICATION ANALYSIS TO ENHANCE A PRODUCTION PROCESS
    8.
    发明申请
    TOOL COMMONALITY AND STRATIFICATION ANALYSIS TO ENHANCE A PRODUCTION PROCESS 有权
    工具共同和分析分析，以提高生产过程

    公开(公告)号：US20110077765A1

    公开(公告)日：2011-03-31

    申请号：US12568083

    申请日：2009-09-28

    申请人： James Rice ,  Dustin K. Slisher ,  Yunsheng Song

    发明人： James Rice ,  Dustin K. Slisher ,  Yunsheng Song

    IPC分类号： G06F19/00

    CPC分类号： G05B23/0294

    摘要： A method of analyzing production steps includes inputting application data associated with a production process having a plurality of process steps into a memory with each of the plurality of process steps including a plurality of tools. The method also includes loading process data associated with one of the plurality of process steps into the memory, performing a tool commonality analysis on each of the tools associated with the at least one of the plurality of process steps, identifying all tool-to-tool differences for the at least one of the plurality of process steps, performing a tool stratification analysis to identify one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps, and stopping the one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps.

    摘要翻译： 分析生产步骤的方法包括将与具有多个处理步骤的生产过程相关联的应用数据输入存储器，其中多个处理步骤中的每一个包括多个工具。 该方法还包括将与多个处理步骤之一相关联的过程数据加载到存储器中，对与多个处理步骤中的至少一个相关联的每个工具执行工具共性分析，识别所有工具对工具 对于所述多个处理步骤中的至少一个处理步骤的差异，执行工具分层分析以识别为所述多个处理步骤中的至少一个处理步骤提供最大变化贡献的所述多个工具之一，并且停止 多个工具，其对多个处理步骤中的至少一个提供最大的方差贡献。