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1.发明授权
公开(公告)号：US4933910A
公开(公告)日：1990-06-12
申请号：US215652
申请日：1988-07-06
IPC分类号： G11C7/10
CPC分类号： G11C7/1021
摘要： Page mode memory access is enabled despite an immediately previous idle cycle. A row address strobe signal is maintained active during an idle cycle so that if a page hit is detected on a subsequent memory cycle, all that is needed to read or write to memory is a column address strobe signal which can be provided via a page mode access. In this manner, memory speed is enhanced because a conventional access is not required on the first memory cycle following one or more idle cycles.
摘要翻译： 页面模式存储器访问启用，尽管紧接在前的空闲周期。 在空闲周期期间，行地址选通信号保持有效，这样如果在随后的存储器周期中检测到页命中，读或写存储器所需的全部是列地址选通信号，可以通过页模式 访问。 以这种方式，存储器速度得到提高，因为在一个或多个空闲周期之后的第一存储器循环中不需要常规访问。
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2.发明授权
公开(公告)号：US4847758A
公开(公告)日：1989-07-11
申请号：US115278
申请日：1987-10-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0884 , G06F12/0862
摘要： A data processing system includes a high speed buffer, or cache, memory for temporarily storing recently executed instructions and a slower main memory in which is stored the system's operating program. Rather than sequentially accessing the cache memory to determine if the next instruction is stored therein and then accessing the main memory if the cache memory does not have the next instruction, system operating speed is increased by simultaneously accessing the cache and main memories. By accessing the main memory during its row address strobe (RAS) precharge time while simultaneously accessing the cache memory, the time necessary for the system's processor unit (PU) to read the next instruction from the main memory when not stored in the cache memory is substantially reduced.
摘要翻译： 数据处理系统包括用于临时存储最近执行的指令的高速缓冲器或高速缓存存储器，以及存储系统的操作程序的较慢的主存储器。 不是顺序地访问高速缓冲存储器以确定下一个指令是否存储在其中，并且如果高速缓冲存储器不具有下一个指令则访问主存储器，则通过同时访问高速缓存和主存储器来增加系统操作速度。 通过在行地址选通（RAS）预充电时间访问主存储器同时访问高速缓冲存储器时，系统处理器单元（PU）在未存储在高速缓冲存储器中时从主存储器读取下一条指令所需的时间是 大大减少。
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3.发明授权Mounting of DRAMs of different sizes and pinouts within limited footprint 失效在有限的占地面积内安装不同尺寸和引脚排列的DRAM
公开(公告)号：US5064378A
公开(公告)日：1991-11-12
申请号：US294925
申请日：1988-12-30
申请人： Anthony M. Olson , Babu Rajaram
发明人： Anthony M. Olson , Babu Rajaram
CPC分类号： H01L25/18 , G11C5/00 , H01L23/50 , H05K1/0295 , H01L2924/0002 , H05K1/11 , H05K1/18 , H05K2201/09954 , H05K2201/10689
摘要： Four parallel, spaced arrays of apertures are provided in a printed circuit (PC) board to accommodate mounting of 16- and 18-pin dynamic random access memories (DRAMs) within a minimum area footprint. First and second 8-aperture linear arrays are provided in the PC board in spaced relation to accommodate 16-pin DRAMs as are third and fourth 9-aperture linear arrays to accommodate 18-pin DRAMs, wherein the third and fourth arrays of apertures are aligned parallel with and respectively positioned intermediate and outside of the first and second arrays of apertures in the PC board. Corresponding apertures in the 16- and 18-aperture arrays for receiving corresponding pins of the 16- and 18- pin DRAMs are electrically coupled, with the two additional apertures of the 18-aperture array extending beyond the 16-aperture array and aligned therewith. The limited footprint area is thus capable of receiving, mounting and electrically coupling in circuit either a 16-pin or an 18-pin DRAM or any integrated circuit having a dual-in-line pinout configuration.
摘要翻译： 在印刷电路（PC）板中提供了四个平行的间隔开的阵列，以适应在最小面积尺寸内安装16和18针动态随机存取存储器（DRAM）。 第一和第二8孔径线性阵列以间隔的关系设置在PC板中，以适应16引脚DRAM，第三和第四个9孔径线阵列可容纳18针DRAM，其中第三和第四孔阵列对准 平行于并分别定位在PC板中的第一和第二孔阵列的中间和外侧。 用于接收16引脚和18引脚DRAM的相应引脚的16和18孔径阵列中的相应的孔电耦合，18孔径阵列的两个附加孔径延伸超过16孔径阵列并与之对齐。 因此，有限的占用面积能够在16引脚或18引脚DRAM或具有双列直插引脚配置的任何集成电路中接收，安装和电耦合。
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公开(公告)号：US4792929A
公开(公告)日：1988-12-20
申请号：US29299
申请日：1987-03-23
申请人： Anthony M. Olson , Babu Rajaram
发明人： Anthony M. Olson , Babu Rajaram
IPC分类号： G11C11/4076 , G11C8/00 , G11C7/00
CPC分类号： G11C11/4076
摘要： A data processing system includes a plurality of memory access devices, each having a characteristic operating speed, for writing data into and reading data from a dynamic random access memory (DRAM) as well as a memory controller for accessing a plurality of addressable storage locations in the DRAM for either storing data in or reading stored data from the various storage locations in the DRAM. The system further includes a dynamic column address strobe (CAS) signal generator responsive to a memory access cycle signal, or READ pulse, and a conventional CAS signal for generating a dynamic CAS signal having a floating trailing edge which extends to the end of the memory access cycle as well as to the trailing edge of the READ pulse irrespective of the length of the memory access cycle signal to allow data to be read from the DRAM by any memory access device regardless of its operating speed during a memory access signal without losing or temporarily storing this data prior to providing it to the memory access device.
摘要翻译： 数据处理系统包括多个存储器访问设备，每个存储器访问设备各自具有特征操作速度，用于将数据写入到动态随机存取存储器（DRAM）中并从其读取数据，以及存储器控制器，用于访问多个可寻址存储位置 用于将数据存储在DRAM中或从DRAM中的各种存储位置读取存储的数据的DRAM。 该系统还包括响应于存储器访问周期信号或READ脉冲的动态列地址选通（CAS）信号发生器和用于生成具有延伸到存储器的末端的浮动后沿的动态CAS信号的常规CAS信号 访问周期以及READ脉冲的后沿，而与存储器访问周期信号的长度无关，以允许任何存储器访问设备从DRAM读取数据，而不管其在存储器访问信号期间的操作速度如何，而不会丢失或 在将其提供给存储器访问设备之前临时存储该数据。
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5.发明授权Variable size queue circuit for buffering data transfers from a processor to a memory 失效用于缓冲从处理器到存储器的数据传输的可变大小的队列电路
公开(公告)号：US5363486A
公开(公告)日：1994-11-08
申请号：US91462
申请日：1993-07-13
申请人： Anthony M. Olson , Babu Rajaram
发明人： Anthony M. Olson , Babu Rajaram
CPC分类号： G06F13/1642
摘要： A computer system includes a memory capable of storing a plurality of data words, and a central processing unit for outputting data words to be stored in the memory. A method and apparatus for facilitating transfer of the data words from the central processing unit to the memory involve accepting and temporarily storing in a storage portion each data word from the central processing unit and then subsequently storing in the memory each temporarily stored data word, the maximum number of data words which can be temporarily stored being selectively set to one of first and second values which are different.
摘要翻译： 计算机系统包括能够存储多个数据字的存储器，以及用于输出要存储在存储器中的数据字的中央处理单元。 一种用于促进将数据字从中央处理单元传送到存储器的方法和装置，包括接收和临时存储来自中央处理单元的每个数据字的存储部分，然后在存储器中存储每个临时存储的数据字， 可以临时存储的最大数量的数据字被选择性地设置为不同的第一和第二值中的一个。
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6.发明授权Method of combining lower order and translated upper order bits to address ROM within a range reserved for other devices 失效将低阶和高阶位转换为在其他设备预留的范围内寻址ROM的方法
公开(公告)号：US5253350A
公开(公告)日：1993-10-12
申请号：US555778
申请日：1990-07-19
申请人： Mark J. Foster , Babu Rajaram , Anthony M. Olson
发明人： Mark J. Foster , Babu Rajaram , Anthony M. Olson
CPC分类号： G06F12/0623
摘要： In response to an address decoded in a preselected range, a multiplexer combines translated high order address bits with CPU-generated low order address bits to access random access memory, especially reserved range random access memory. Otherwise, the multiplexer merely combines CPU-generated low order bits with CPU-generated high order address bits to access RAM. An expanded memory specification memory map drives the translator to generate the translated high order address bits. This generates the address for reserved range RAM. RAM contents, normal and reserved range, are available for processing by the CPU.
摘要翻译： 响应于以预选范围解码的地址，多路复用器将转换后的高阶地址位与CPU生成的低位地址位组合以访问随机存取存储器，特别是预留范围随机存取存储器。 否则，多路复用器仅将CPU生成的低位位与CPU生成的高位地址位组合以访问RAM。 扩展的存储器规范存储器映射驱动转换器以产生转换的高位地址位。 这将产生预留范围RAM的地址。 RAM内容，正常和保留范围可供CPU处理。
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公开(公告)号：US4703419A
公开(公告)日：1987-10-27
申请号：US886956
申请日：1986-07-24
CPC分类号： G06F15/17
摘要： In a dual microprocessor system, a processor transfer, or swap, arrangement and method therefor are disclosed for transferring control from one processor to another. The present invention involves the temporary suspension of operation of a first microprocessor which relinquishes system control and the initiation of operation of a second microprocessor which may begin operation either where it last left off or may execute a new operating routine in accordance with instructions provided by the first microprocessor. Provision is made for automatically handing over system control to the second microprocessor upon the occurrence of an interrupt. In addition, the microprocessor not exercising system control is rendered unresponsive to the occurrence of a program interrupt allowing it to continue opration unaffected by the program interrupt following its reactivation. -
摘要翻译： 在双微处理器系统中，公开了一种用于将控制从一个处理器传送到另一处理器的处理器传送或其交换，布置和方法。 本发明涉及第一微处理器的暂时停止操作，该第一微处理器放弃了系统控制和第二微处理器的操作，该第二微处理器可以在其最后一次停止时开始操作，或者可以根据由该控制器提供的指令执行新的操作程序 第一个微处理器 提供了在发生中断时自动将系统控制移交给第二个微处理器。 另外，不执行系统控制的微处理器对程序中断的发生没有反应，允许它在其重新激活之后继续执行程序中断所影响的操作。
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公开(公告)号：US4620186A
公开(公告)日：1986-10-28
申请号：US527943
申请日：1983-08-30
申请人： Charles A. Krause , Babu Rajaram
发明人： Charles A. Krause , Babu Rajaram
CPC分类号： G09G5/022
摘要： In a video display system having a video random access memory (RAM) including a plurality of color memory banks, with one memory bank for each of the primary colors, provision is made for simultaneously writing to all of the color banks. A central processor unit (CPU) places data onto the system bus and asserts WRT-R, WRT-G and/or WRT-B signals in selectively writing at the same time to any or all of the video RAM banks, where the primary colors are red, green and blue. Logic circuitry coupled to the three RAM banks then gates designated Row and Column Address Strobe (RAS and CAS) signals to each of the color arrays followed by color video data signals. The time required to thus write video display information into the multi-bank video RAM array is thus reduced and system video data throughput correspondingly increased.
摘要翻译： 在具有包括多个彩色存储器组的视频随机存取存储器（RAM）的视频显示系统中，具有用于每种原色的一个存储体组，用于同时写入所有彩色组。 中央处理器单元（CPU）将数据放置在系统总线上，并且将所有或所有视频RAM同时选择性地写入，并且断言和上拉W＆amp; upbar＆R，＆upbar＆W-＆upbar＆G和/或＆upbar＆W-＆upbar＆B信号 银行，原色是红色，绿色和蓝色。 耦合到三个RAM组的逻辑电路然后将指定的行和列地址选通（RAS和CAS）信号锁定到每个彩色阵列，随后是彩色视频数据信号。 因此，将视频显示信息写入多存储体视频RAM阵列所需的时间因此减少，并且系统视频数据吞吐量相应增加。
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公开(公告)号：US4594587A
公开(公告)日：1986-06-10
申请号：US527945
申请日：1983-08-30
申请人： Gregg Chandler , Babu Rajaram
发明人： Gregg Chandler , Babu Rajaram
摘要： Conventional bit-mapped address locations in a character oriented video random access memory (RAM) in which each character is represented by a bit mapping array comprised of ten lines each including eight pixels, or eight bits of information, in an X-Y matrix address organization are redefined in terms of the character and row address locations of a graphics oriented cathode ray tube controller for driving a video display. Groups of bits in the X-Y matrix address locations of the video RAM are shifted in a predetermined manner in generating a redefined, 1:1 mapping function addressing code which is provided to a cathode ray tube controller for driving the video display. A video RAM mapping module is provided for reorganizing the video RAM addresses and translating these addresses throughout the page of the video RAM in providing more efficient graphics mapping while retaining high resolution alphanumeric character video resolution. In one embodiment, a video display start bit is incremented by an 8-bit adder to provide for scrolling on a line-by-line basis without moving character bytes from one location to another in the video RAM.
摘要翻译： 字符定向视频随机存取存储器（RAM）中的常规位映射地址位置，其中每个字符由在XY矩阵地址组织中包括八个像素或八位信息的十行构成的位映射阵列表示， 根据用于驱动视频显示器的图形取向阴极射线管控制器的字符和行地址位置重新定义。 视频RAM的X-Y矩阵地址位置中的位组以预定的方式移位，以产生提供给用于驱动视频显示的阴极射线管控制器的重新定义的1：1映射函数寻址码。 提供了视频RAM映射模块，用于重新组织视频RAM地址，并在视频RAM的整个页面上翻译这些地址，以提供更有效的图形映射，同时保持高分辨率的字母数字字符视频分辨率。 在一个实施例中，视频显示开始位由8位加法器递增，以在逐行基础上提供滚动，而不会在视频RAM中从一个位置移动字符字节到另一个位置。
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公开(公告)号：US4574277A
公开(公告)日：1986-03-04
申请号：US527944
申请日：1983-08-30
申请人： Charles A. Krause , Babu Rajaram
发明人： Charles A. Krause , Babu Rajaram
CPC分类号： G09G5/022
摘要： A video display system utilizes three banks of memory for producing an 8-color or an 8-level gray scale display. A separate memory plane, or random access memory (RAM) array, for each of the "primary" video colors, i.e., red, green and blue, is used in a bit-mapped video graphics implementation for a computer driven video display. In a monochrome display, pixel mixing produces the 8-level gray scale display. Each of the video planes may be selectively disabled as desired for special applications. For example, a limited animation capability may be provided by displaying one page while generating a new page in a non-displayed page. By disabling the currently displayed plane as the new plane is enabled, instantaneous page modification may be closely simulated for animated applications. The thus disabled video plane may then be used as any normal page of RAM for any other application. In addition, all of the video RAM planes may be disengaged from the central processing unit (CPU) to blank the video display for various applications such as during initial system reset or as part of an operating program.
摘要翻译： 视频显示系统利用三组存储器来产生8色或8级灰阶显示。 对于用于计算机驱动的视频显示的位映射视频图形实现，使用用于“主”视频颜色（即，红色，绿色和蓝色）中的每一种的单独的存储器平面或随机存取存储器（RAM）阵列。 在单色显示中，像素混合产生8级灰阶显示。 可以根据需要选择性地禁用每个视频平面用于特殊应用。 例如，可以通过在非显示页面中生成新页面的同时显示一个页面来提供有限的动画功能。 通过在启用新平面时禁用当前显示的平面，可以为动画应用程序密切模拟即时页面修改。 因此，如此禁用的视频平面可以用作任何其他应用的RAM的任何正常页面。 此外，所有视频RAM平面可以与中央处理单元（CPU）脱离，以便在诸如初始系统复位期间或作为操作程序的一部分的各种应用中消除视频显示。
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