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公开(公告)号：US07135907B2
公开(公告)日：2006-11-14
申请号：US11255707
申请日：2005-10-21
申请人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
发明人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.
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公开(公告)号：US07071757B2
公开(公告)日：2006-07-04
申请号：US09682473
申请日：2001-09-06
申请人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
发明人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.
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公开(公告)号：US06479974B2
公开(公告)日：2002-11-12
申请号：US09750884
申请日：2000-12-28
申请人： John Maxwell Cohn , Alvar Antonio Dean , David James Hathaway , Patrick Edward Perry , Sebastian Theodore Ventrone
发明人： John Maxwell Cohn , Alvar Antonio Dean , David James Hathaway , Patrick Edward Perry , Sebastian Theodore Ventrone
IPC分类号： G05F304
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.
摘要翻译： 一种用于提供片上电压分配和调节的系统和方法。 根据本发明的系统，IC芯片包括具有用于向IC芯片供电的源极电源轨的源极电压平面和用于从其供电的电力的源极接地导轨。 至少一个中间接地轨连接在源电源轨和源极接地轨之间，以将源电压平面分成多个中间电压平面。 中间接地导轨用作后续中间电压平面的电源轨，使得中间电压平面串联连接。
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公开(公告)号：US06345362B1
公开(公告)日：2002-02-05
申请号：US09287173
申请日：1999-04-06
申请人： Claude Louis Bertin , Alvar Antonio Dean , Kenneth Joseph Goodnow , Scott Whitney Gould , Wilbur David Pricer , William Robert Tonti , Sebastian Theodore Ventrone
发明人： Claude Louis Bertin , Alvar Antonio Dean , Kenneth Joseph Goodnow , Scott Whitney Gould , Wilbur David Pricer , William Robert Tonti , Sebastian Theodore Ventrone
IPC分类号： G06F132
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F9/3867 , G06F9/3869 , Y02D10/126 , Y02D10/171
摘要： An integrated circuit includes a CPU, a power management unit and plural functional units each dedicated to executing different functions. The power management unit controls the threshold voltage of the different functional units to optimize power/performance operation of the circuit and intelligent power management control responds to the instruction stream and decodes each instruction in turn. This information identifies which of the functional units are required for the particular instruction and by comparing that information to power status, the intelligent power control determines whether the functional units required to execute the command are at the optimum power level. If they are, the command is allowed to proceed, otherwise the intelligent power control either stalls the instruction sequence or modifies process speed.
摘要翻译： 集成电路包括CPU，电源管理单元和专用于执行不同功能的多个功能单元。 电源管理单元控制不同功能单元的阈值电压，以优化电路的功率/性能运行，智能电源管理控制响应指令流并依次对每条指令进行解码。 该信息识别特定指令需要哪个功能单元，并且通过将该信息与功率状态进行比较，智能功率控制确定执行命令所需的功能单元是否处于最佳功率级。 如果是，则允许该命令继续进行，否则智能功率控制将停止指令序列或修改处理速度。
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5.发明授权Managing VT for reduced power using power setting commands in the instruction stream 失效使用指令流中的电源设置命令管理VT以降低功耗公开(公告)号：US06477654B1
公开(公告)日：2002-11-05
申请号：US09287159
申请日：1999-04-06
IPC分类号： G06F132
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F8/4432 , G06F9/3867 , Y02D10/152 , Y02D10/171 , Y02D10/172 , Y02D10/24 , Y02D10/41
摘要： An integrated circuit includes a plurality of functional units which are capable of operating at more than one power/performance level and a power control unit. The power control unit controls the power/performance consumption of the different functional units to optimize operation of the integrated circuit. Special power control instructions are added to user applications in order to control via the power control unit, the power consumption of the different functional units.
摘要翻译： 集成电路包括能够以多于一个功率/性能水平操作的多个功能单元和功率控制单元。 功率控制单元控制不同功能单元的功率/性能消耗，以优化集成电路的运行。 特殊功率控制指令被添加到用户应用中，以通过功率控制单元控制不同功能单元的功耗。
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公开(公告)号：US06425109B1
公开(公告)日：2002-07-23
申请号：US09360384
申请日：1999-07-23
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A system and method for interconnecting a plurality of cores into a single functional core. The method involves creating for each core a pin configuration structure based on a set of configuration rules. When the cores to be interconnected are selected, the pin configuration structure is accessed by the configurator program tool of the present invention. The configurator program tool then connects the cores together using the pin configuration structure and configuration rules for the selected cores. The configurator program tool generates an error-free high level model of the interconnected cores. The configurator program tool allows configuration flexibility and is general enough to handle most configuration scenarios. The tool is also easy to code, extensible, and can be applied to existing core designs with no modification of the cores themselves.
摘要翻译： 一种用于将多个核心互连成单个功能核心的系统和方法。 该方法包括基于一组配置规则为每个核心创建引脚配置结构。 当选择要互连的芯时，通过本发明的配置程序工具访问引脚配置结构。 然后，配置程序工具使用所选核心的引脚配置结构和配置规则将内核连接在一起。 配置程序工具生成互连核心的无错误高级模型。 配置程序工具允许配置灵活性，并且足以处理大多数配置场景。 该工具也易于编码，可扩展，并且可以应用于现有的核心设计，而不改变内核本身。
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7.发明授权Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode 有权使用低功耗模式降低集成半导体器件功耗的装置和方法
公开(公告)号：US6097243A
公开(公告)日：2000-08-01
申请号：US159861
申请日：1998-09-24
申请人： Claude L. Bertin , William Robert Patrick Tonti , Alvar Antonio Dean , Wilbur David Pricer , Patrick Edward Perry , Kenneth J. Goodnow , Sebastian T. Ventrone
发明人： Claude L. Bertin , William Robert Patrick Tonti , Alvar Antonio Dean , Wilbur David Pricer , Patrick Edward Perry , Kenneth J. Goodnow , Sebastian T. Ventrone
CPC分类号： G06F1/3203 , G06F1/3296 , Y02B60/1285
摘要： According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.
摘要翻译： 根据优选实施例，提供了一种通过减少不需要的节点切换来降低功耗的装置和方法。 优选实施例通过利用上拉或下拉晶体管将电路中的输入引导到在电路不活动的时段期间最小化功耗的状态来减少电路中的不需要的节点切换。 通过在不活动状态下将电路输入高或低，在该电路中节点切换被减少或消除。 在优选实施例中，电路的输入在与电路中最漏电晶体管的漏电流成比例的不活动时间之后全部被拉。 通过定时输入拉动与泄漏电流成比例，最大限度地减少功耗，而不会由拉动本身引起的功率损耗过大。
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公开(公告)号：US06433618B1
公开(公告)日：2002-08-13
申请号：US09146834
申请日：1998-09-03
IPC分类号： G05F110
CPC分类号： H01L27/088
摘要： A variable power device circuit includes a plurality of devices for driving a load. Each of the devices has a body, which is electrically isolated from the substrate. All of the devices are coupled to an output node. The load is also coupled to the output node. A controller selectively turns on individual or multiple ones of the devices based on the electrical requirements of the load.
摘要翻译： 可变功率器件电路包括用于驱动负载的多个器件。 每个装置具有与基板电隔离的主体。 所有设备都耦合到输出节点。 负载也耦合到输出节点。 控制器基于负载的电气要求选择性地打开单个或多个设备。
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