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    Stacked voltage rails for low-voltage DC distribution
    1.
    发明授权
    Stacked voltage rails for low-voltage DC distribution 失效
    用于低压直流分配的堆叠电压轨

    公开(公告)号：US06479974B2

    公开(公告)日：2002-11-12

    申请号：US09750884

    申请日：2000-12-28

    申请人： John Maxwell Cohn ,  Alvar Antonio Dean ,  David James Hathaway ,  Patrick Edward Perry ,  Sebastian Theodore Ventrone

    发明人： John Maxwell Cohn ,  Alvar Antonio Dean ,  David James Hathaway ,  Patrick Edward Perry ,  Sebastian Theodore Ventrone

    IPC分类号： G05F304

    CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

    摘要翻译： 一种用于提供片上电压分配和调节的系统和方法。 根据本发明的系统，IC芯片包括具有用于向IC芯片供电的源极电源轨的源极电压平面和用于从其供电的电力的源极接地导轨。 至少一个中间接地轨连接在源电源轨和源极接地轨之间，以将源电压平面分成多个中间电压平面。 中间接地导轨用作后续中间电压平面的电源轨，使得中间电压平面串联连接。

    True/complement output bus for reduced simulataneous switching noise
    4.
    发明授权
    True/complement output bus for reduced simulataneous switching noise 失效
    用于减少模拟开关噪声的真/补输出总线

    公开(公告)号：US5874833A

    公开(公告)日：1999-02-23

    申请号：US794041

    申请日：1997-02-03

    申请人： Patrick Edward Perry ,  Sebastian Theodore Ventrone

    发明人： Patrick Edward Perry ,  Sebastian Theodore Ventrone

    IPC分类号： H03K19/003 ,  H03K19/0175

    CPC分类号： H03K19/00346

    摘要： A true/complement integrated circuit device is disclosed for reducing an amount of simultaneous switching on a bus between a current state and a next state. The device includes a current state register connected to the bus for outputting the current state onto the bus during a first clock cycle. A next state register is provided for containing the next state, wherein the next state is a pending state of the bus intended for a next clock cycle. A comparison circuit compares a current state value in the current state register with a next state value in the next state register on a bit-by-bit basis to determine if the current state value and the next state value are of a same polarity or of an opposite polarity. A circuit is provided for determining a ratio of switching signals from an output of the bit-by-bit comparisons by the comparison circuit. The ratio determining circuit further generates a true/complement (T/C) signal having a first state if it is determined that more than a prescribed percentage of bits are in transition, the T/C signal having a second state otherwise. Lastly, a circuit is provided for complementing the bits of the next state register in response to the T/C signal being in the first state, and not complementing the bits of the next state register in response to the T/C signal being in the second state, prior to being transferred into the current state register and output onto the bus during the next clock cycle.

    摘要翻译： 公开了一种真/补体集成电路装置，用于减少在当前状态和下一状态之间的总线上的同时开关量。 该装置包括连接到总线的当前状态寄存器，用于在第一时钟周期期间将当前状态输出到总线上。 提供下一个状态寄存器用于包含下一个状态，其中下一个状态是下一个时钟周期的总线的待处理状态。 比较电路将当前状态寄存器中的当前状态值与下一状态寄存器中的下一状态值逐位进行比较，以确定当前状态值和下一状态值是否具有相同的极性，或者 相反的极性。 提供了一种电路，用于确定比较电路中逐位比较输出的开关信号的比例。 比例确定电路进一步产生具有第一状态的真/补（T / C）信号，如果确定多于一定比例的位正在转换，否则T / C信号具有第二状态。 最后，提供一个电路来补偿下一个状态寄存器的位，以响应于T / C信号处于第一状态，并且不响应于T / C信号位于下一个状态寄存器的位 第二状态，在被转移到当前状态寄存器之前，并且在下一个时钟周期内输出到总线上。

    Method and apparatus for reducing power consumption in VLSI circuit designs
    5.
    发明授权
    Method and apparatus for reducing power consumption in VLSI circuit designs 失效
    用于降低VLSI电路设计中的功耗的方法和装置

    公开(公告)号：US06711719B2

    公开(公告)日：2004-03-23

    申请号：US09928573

    申请日：2001-08-13

    申请人： John Maxwell Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas Michael Lepsic ,  Patrick Edward Perry ,  Scott A. Tetreault ,  Sebastian T. Ventrone

    发明人： John Maxwell Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas Michael Lepsic ,  Patrick Edward Perry ,  Scott A. Tetreault ,  Sebastian T. Ventrone

    IPC分类号： G06F1750

    CPC分类号： G06F17/505 ,  G06F2217/78

    摘要： In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

    摘要翻译： 在集成电路（IC）设计中，功率消耗的分量可以表示为功率=½FCV <2>，其中C是由源单元驱动的负载电容，F是源单元的开关频率，V 是总输出电压摆幅。 然而，不是由源单元产生的每个信号值都不需要传播到芯片的每个时钟周期连接到源的所有宿单元。 因此，将隔离单元插入到将源单元连接到至少一个宿单元的网络（有线）中，以便当由所述源单元输出的信号从所述源单元输出时，将所述至少一个宿单元和所述网的一部分与所述源单元分离 源不需要传播。 由于去耦合，与至少一个接收器和净部分相关联的负载电容对于这种信号不被源单元体验。 因此，整体IC功耗降低。

    Redundant vias
    6.
    发明授权
    Redundant vias 失效
    冗余通孔

    公开(公告)号：US6026224A

    公开(公告)日：2000-02-15

    申请号：US753137

    申请日：1996-11-20

    申请人： Laura Rohwedder Darden ,  William John Livingstone ,  Jeannie Harrigan Panner ,  Patrick Edward Perry ,  William Frank Pokorny ,  Paul Steven Zuchowski

    发明人： Laura Rohwedder Darden ,  William John Livingstone ,  Jeannie Harrigan Panner ,  Patrick Edward Perry ,  William Frank Pokorny ,  Paul Steven Zuchowski

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

    摘要： A wiring design tool which detects minimum area vias and replaces them with redundant vias pairs. The invention uses the definitions for single vias and tracks in a grid coordinate system and a file describing the design wires and their interconnections to select the most favorable direction for the placement. The invention accomplishes this by examining the directions one track away from each single via at various levels and according to the methodology of this invention, detects a possible situs for a redundant via pair, preferably where a segment of wire on the same net already exists. If no design rule violation occurs the system replaces the single via with a redundant via pair.

    摘要翻译： 一种接线设计工具，用于检测最小面积通孔，并用冗余通孔对代替它们。 本发明使用网格坐标系中的单个通孔和轨道的定义以及描述设计线及其互连的文件来选择最有利的放置方向。 本发明通过检查在各个级别上离开每个单个通道一个轨迹的方向来实现这一点，并且根据本发明的方法，检测冗余通路对的可能的位置，优选地，其中已经存在同一网络上的一段电线。 如果没有设计规则违规，系统将使用冗余通路对替换单个通道。