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    FRACTIONAL DIVIDER FOR AVOIDANCE OF LC-VCO INTERFERENCE AND JITTER
    1.
    发明申请
    FRACTIONAL DIVIDER FOR AVOIDANCE OF LC-VCO INTERFERENCE AND JITTER 有权
    用于避免LC-VCO干扰和抖动的分路器

    公开(公告)号：US20120268177A1

    公开(公告)日：2012-10-25

    申请号：US13450280

    申请日：2012-04-18

    申请人： John Hogeboom ,  Pat Hogeboom-Nivera ,  Anton Pelteshki

    发明人： John Hogeboom ,  Pat Hogeboom-Nivera ,  Anton Pelteshki

    IPC分类号： H03L7/08

    CPC分类号： H03L7/23 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1974 ,  H03L7/24

    摘要： A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.

    摘要翻译： 用于避免比特率干扰的分数速率LC VCO和补偿分频器电路包括具有用于接收参考时钟信号的输入的LC PLL，具有耦合到LC PLL的输出的输入的具有旋转注入的N级环形VCO，以及 用于提供输出时钟信号的输出，具有耦合到N级环形VCO的输出的输入和耦合到LC PLL的输出的第一分频器电路，具有耦合到LC的输出的输入的第二分频器电路 PLL和M级参考环PLL，其具有耦合到第二分频器的输出的输入端和耦合到N级环形VCO的输出。

    TRANSMIT DRIVER CIRCUIT
    6.
    发明申请
    TRANSMIT DRIVER CIRCUIT 有权
    发射驱动电路

    公开(公告)号：US20130002311A1

    公开(公告)日：2013-01-03

    申请号：US13333729

    申请日：2011-12-21

    申请人： Anton Pelteshki ,  Hock Khor

    发明人： Anton Pelteshki ,  Hock Khor

    IPC分类号： H03K3/00

    CPC分类号： H03K3/01 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2203/45394 ,  H03F2203/45712 ,  H04L25/0266 ,  H04L25/0276 ,  H04L25/0282

    摘要： A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.

    摘要翻译： 驱动器电路包括差分输入，差分输出，偏置节点，具有耦合到负输出节点的第一节点的第一T形线圈和耦合到电源电压源的第二节点，第二T形线圈具有 耦合到正输出节点的第一节点和耦合到电源电压源的第二节点，具有耦合在第一T形线圈的中心抽头和第一中间节点之间的电流通路的第一晶体管，具有电流 耦合在第二T形线圈的中心抽头和第二中间节点之间的路径，具有耦合在第一中间节点和地之间的电流路径的第三晶体管，以及连接在第二中间节点和地之间的电流路径的第四晶体管 。

    Fractional divider for avoidance of LC-VCO interference and jitter
    7.
    发明授权
    Fractional divider for avoidance of LC-VCO interference and jitter 有权
    用于避免LC-VCO干扰和抖动的分数分频器

    公开(公告)号：US08754682B2

    公开(公告)日：2014-06-17

    申请号：US13450280

    申请日：2012-04-18

    申请人： Anton Pelteshki ,  Pat Hogeboom-Nivera

    发明人： John Hogeboom ,  Anton Pelteshki

    IPC分类号： H03L7/06

    CPC分类号： H03L7/23 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1974 ,  H03L7/24

    摘要： A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.

    摘要翻译： 用于避免比特率干扰的分数速率LC VCO和补偿分频器电路包括具有用于接收参考时钟信号的输入的LC PLL，具有耦合到LC PLL的输出的输入的具有旋转注入的N级环形VCO，以及 用于提供输出时钟信号的输出，具有耦合到N级环形VCO的输出的输入和耦合到LC PLL的输出的第一分频器电路，具有耦合到LC的输出的输入的第二分频器电路 PLL和M级参考环PLL，其具有耦合到第二分频器的输出的输入端和耦合到N级环形VCO的输出。

    Transmit driver circuit
    8.
    发明授权
    Transmit driver circuit 有权
    发射驱动电路

    公开(公告)号：US08587348B2

    公开(公告)日：2013-11-19

    申请号：US13333729

    申请日：2011-12-21

    申请人： Anton Pelteshki ,  Hock Khor

    发明人： Anton Pelteshki ,  Hock Khor

    IPC分类号： H03B1/00

    CPC分类号： H03K3/01 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2203/45394 ,  H03F2203/45712 ,  H04L25/0266 ,  H04L25/0276 ,  H04L25/0282

    摘要： A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.

    摘要翻译： 驱动器电路包括差分输入，差分输出，偏置节点，具有耦合到负输出节点的第一节点的第一T形线圈和耦合到电源电压源的第二节点，第二T形线圈具有 耦合到正输出节点的第一节点和耦合到电源电压源的第二节点，具有耦合在第一T形线圈的中心抽头和第一中间节点之间的电流通路的第一晶体管，具有电流 耦合在第二T形线圈的中心抽头和第二中间节点之间的路径，具有耦合在第一中间节点和地之间的电流路径的第三晶体管，以及连接在第二中间节点和地之间的电流路径的第四晶体管 。