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1.发明申请CIRCUIT AND METHOD FOR GENERATING A REFERENCE VOLTAGE IN MEMORY DEVICES HAVING A NON-VOLATILE CELL MATRIX 有权在具有非易失性单元矩阵的存储器件中产生参考电压的电路和方法公开(公告)号：US20080130361A1
公开(公告)日：2008-06-05
申请号：US11941688
申请日：2007-11-16
申请人： Antonino Conte , Mario Micciche , Gianbattista Lo Giudice , Alberto Di Martino , Giampiero Sberno
发明人： Antonino Conte , Mario Micciche , Gianbattista Lo Giudice , Alberto Di Martino , Giampiero Sberno
CPC分类号： G11C16/30
摘要： A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.
摘要翻译： 发电机电路在连接到非易失性存储器单元矩阵的输出端上产生参考电压，并且包括位于公共节点和输出端之间的比较器。 比较器具有第一和第二输入端子和适于提供通过比较第一和第二输入端子上存在的第一和第二电压值给出的比较电压的输出端子。 电路包括插入公共节点和第一电压基准之间的参考单元。 有利地，参考单元包括具有耦合到偏置块的接触端子的浮动栅极，其具有连接到发生器电路的输出端子的输入端子，并且适于在第二个偏置电压周期性地偏置浮置栅极接触端子 电压参考。
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2.发明授权Circuit and method for generating a reference voltage in memory devices having a non-volatile cell matrix 有权用于在具有非易失性单元矩阵的存储器件中产生参考电压的电路和方法公开(公告)号：US07633805B2
公开(公告)日：2009-12-15
申请号：US11941688
申请日：2007-11-16
申请人： Antonino Conte , Mario Micciche , Gianbattista Lo Giudice , Alberto Di Martino , Giampiero Sberno
发明人： Antonino Conte , Mario Micciche , Gianbattista Lo Giudice , Alberto Di Martino , Giampiero Sberno
IPC分类号： G11C11/34
CPC分类号： G11C16/30
摘要： A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.
摘要翻译： 发电机电路在连接到非易失性存储器单元矩阵的输出端上产生参考电压，并且包括位于公共节点和输出端之间的比较器。 比较器具有第一和第二输入端子和适于提供通过比较第一和第二输入端子上存在的第一和第二电压值给出的比较电压的输出端子。 电路包括插入公共节点和第一电压基准之间的参考单元。 有利地，参考单元包括具有耦合到偏置块的接触端子的浮动栅极，其具有连接到发生器电路的输出端子的输入端子，并且适于在第二个偏置电压周期性地偏置浮置栅极接触端子 电压参考。
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3.发明申请SENSE-AMPLIFIER CIRCUIT FOR NON-VOLATILE MEMORIES THAT OPERATES AT LOW SUPPLY VOLTAGES 有权用于低电压下运行的非易失性存储器的感应放大器电路公开(公告)号：US20110069554A1
公开(公告)日：2011-03-24
申请号：US12883072
申请日：2010-09-15
IPC分类号： G11C16/06
摘要： A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.
摘要翻译： 感测放大器电路包括：比较级，其将存储单元中流动的单元电流和相关联的位线与参考电流进行比较，用于提供指示存储单元的状态的输出信号; 以及预充电阶段，其在比较步骤之前的预充电步骤期间向位线提供预充电电流以对其电容充电。 比较级包括第一比较晶体管和第二比较晶体管，其以电流镜配置分别耦合到第一差分输出和偏置电流流过的第二差分输出。 预充电阶段在预充电步骤期间将作为预充电电流的朝向位线的偏置电流转移，并且在比较步骤期间允许偏置电流的一部分朝向第一差分输出通过，使得能够操作电流镜。
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4.发明授权Sense-amplifier circuit for non-volatile memories that operates at low supply voltages 有权用于在低电源电压下工作的非易失性存储器的感应放大器电路公开(公告)号：US08437196B2
公开(公告)日：2013-05-07
申请号：US12883072
申请日：2010-09-15
IPC分类号： G11C16/06
摘要： A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.
摘要翻译： 感测放大器电路包括：比较级，其将存储单元中流动的单元电流和相关联的位线与参考电流进行比较，用于提供指示存储单元的状态的输出信号; 以及预充电阶段，其在比较步骤之前的预充电步骤期间向位线提供预充电电流以对其电容充电。 比较级包括第一比较晶体管和第二比较晶体管，其以电流镜配置分别耦合到第一差分输出和偏置电流流过的第二差分输出。 预充电阶段在预充电步骤期间将作为预充电电流的朝向位线的偏置电流转移，并且在比较步骤期间允许偏置电流的一部分朝向第一差分输出通过，使得能够操作电流镜。
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5.发明授权Method for biasing an EEPROM non-volatile memory array and corresponding EEPROM non-volatile memory device 有权用于偏置EEPROM非易失性存储器阵列和相应的EEPROM非易失性存储器件的方法公开(公告)号：US08376237B2
公开(公告)日：2013-02-19
申请号：US12885028
申请日：2010-09-17
IPC分类号： G06K19/06
CPC分类号： G11C16/0433 , G11C16/10 , G11C16/16
摘要： Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation.
摘要翻译： 这里描述了一种用于偏置由排列成行和列的存储器单元形成的EEPROM阵列的方法，每个可操作地耦合到第一开关和第二开关，并且具有通过第一开关选择性地连接到位线的第一导通端子， 选择性地可连接到通过第二开关的栅极控制线的控制终端，其中与每一行相关联的是分别连接到第一开关的控制端的第一字线和第二字线，以及分别操作地耦合到 同一行的存储单元。 该方法设想为给定的存储器操作选择至少一个存储器单元，偏置与其相关联的行的第一字线和第二字线，并且特别是以彼此不同的电压偏置第一和第二字线并且具有更高的值 而不是内部电源电压，并且是给定存储器操作的函数。
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公开(公告)号：US20080007321A1
公开(公告)日：2008-01-10
申请号：US11771157
申请日：2007-06-29
IPC分类号： G05F1/10
摘要： An integrated control circuit for a charge pump includes a first device for regulating the output voltage of the charge pump and a second device for increasing the output voltage from the charge pump with a set ramp. The integrated circuit includes means for activating said first device and providing it with a first value of a supply signal in a first period of time and for activating the second device and providing it with a second value of the supply signal that is greater than the first value in a second period of time after the first in such a way that the output voltage of the charge pump ascends a ramp from a first value to a second value that is greater than the first value, the second value being fixed by reactivation of the first device.
摘要翻译： 用于电荷泵的集成控制电路包括用于调节电荷泵的输出电压的第一装置和用于通过设定斜坡增加来自电荷泵的输出电压的第二装置。 集成电路包括用于激活所述第一设备并且在第一时间段内向其提供电源信号的第一值并且用于激活第二设备并且向其提供大于第一设备的第二电源信号的第二值的装置 在第一次之后的第二时间段内的值以使得电荷泵的输出电压从第一值升高到大于第一值的第二值的斜坡，第二值通过重新激活固定 第一个装置
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7.发明授权Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, useful in low supply-voltage technologies 有权用于读取和验证电可编程和可擦除非易失性存储器单元的内容的感测电路，可用于低电源电压技术公开(公告)号：US06906957B2
公开(公告)日：2005-06-14
申请号：US10662151
申请日：2003-09-12
CPC分类号： G11C16/28
摘要： Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
摘要翻译： 用于读取和验证电可编程和可擦除非易失性存储单元的内容的感测电路包括读出放大器，其具有连接到要读取的单元的第一感测电路部分，并且具有用于连接到第一输入端的第一输入端的输出端 比较器，并具有连接到参考电流发生器的第二参考电路部分，并且具有用于连接到所述比较器的第二输入端子的输出端子，其特征在于，所述第一和所述第二电路部分包括一系列第一和第二 晶体管分别连接在第一参考电压和第二电压基准之间，并且具有连接到所述第一和第二电路部分的所述输出端子的互连互连点。
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8.发明申请METHOD FOR BIASING AN EEPROM NON-VOLATILE MEMORY ARRAY AND CORRESPONDING EEPROM NON-VOLATILE MEMORY DEVICE 有权用于偏移EEPROM非易失性存储器阵列和对应EEPROM非易失性存储器件的方法公开(公告)号：US20110068179A1
公开(公告)日：2011-03-24
申请号：US12885028
申请日：2010-09-17
IPC分类号： G06K19/073 , G11C16/14 , G11C16/12
CPC分类号： G11C16/0433 , G11C16/10 , G11C16/16
摘要： Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation.
摘要翻译： 这里描述了一种用于偏置由排列成行和列的存储器单元形成的EEPROM阵列的方法，每个可操作地耦合到第一开关和第二开关，并且具有通过第一开关选择性地连接到位线的第一导通端子， 选择性地可连接到通过第二开关的栅极控制线的控制终端，其中与每一行相关联的是分别连接到第一开关的控制端的第一字线和第二字线，以及分别操作地耦合到 同一行的存储单元。 该方法设想为给定的存储器操作选择至少一个存储器单元，偏置与其相关联的行的第一字线和第二字线，并且特别是以彼此不同的电压偏置第一和第二字线并且具有更高的值 而不是内部电源电压，并且是给定存储器操作的函数。
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公开(公告)号：US07602230B2
公开(公告)日：2009-10-13
申请号：US11771157
申请日：2007-06-29
IPC分类号： H03K3/01
摘要： An integrated control circuit for a charge pump includes a first device for regulating the output voltage of the charge pump and a second device for increasing the output voltage from the charge pump with a set ramp. The integrated circuit includes means for activating said first device and providing it with a first value of a supply signal in a first period of time and for activating the second device and providing it with a second value of the supply signal that is greater than the first value in a second period of time after the first in such a way that the output voltage of the charge pump ascends a ramp from a first value to a second value that is greater than the first value, the second value being fixed by reactivation of the first device.
摘要翻译： 用于电荷泵的集成控制电路包括用于调节电荷泵的输出电压的第一装置和用于通过设定斜坡增加来自电荷泵的输出电压的第二装置。 集成电路包括用于激活所述第一设备并且在第一时间段内向其提供电源信号的第一值并且用于激活第二设备并且向其提供大于第一设备的第二电源信号的第二值的装置 在第一次之后的第二时间段内的值以使得电荷泵的输出电压从第一值升高到大于第一值的第二值的斜坡，第二值通过重新激活固定 第一个装置
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10.发明授权Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, useful in low supply-voltage technologies 有权用于读取和验证电可编程和可擦除非易失性存储器单元的内容的感测电路，可用于低电源电压技术公开(公告)号：US06704233B2
公开(公告)日：2004-03-09
申请号：US10171508
申请日：2002-06-12
IPC分类号： G11C700
CPC分类号： G11C16/28
摘要： Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells including a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
摘要翻译： 用于读取和验证电可编程和可擦除非易失性存储单元的内容的感测电路，包括读出放大器，该读出放大器具有连接到要读取的单元的第一感测电路部分，并且具有用于连接到第一输入端的输出端 比较器，并且具有连接到参考电流发生器的第二参考电路部分，并且具有用于连接到所述比较器的第二输入端的输出端，其特征在于，所述第一和所述第二电路部分包括一系列第一和第二晶体管 分别连接在第一参考电压和第二电压基准之间，并且具有连接到所述第一和第二电路部分的所述输出端子的互连点。
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