公开(公告)号：US20070150771A1

公开(公告)日：2007-06-28

申请号：US11314737

申请日：2005-12-22

申请人： Antony Penton ,  Vladimir Vasekin ,  Andrew Rose ,  Paul Hughes ,  Christopher Wrigley

发明人： Antony Penton ,  Vladimir Vasekin ,  Andrew Rose ,  Paul Hughes ,  Christopher Wrigley

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： A data processing apparatus comprising a plurality of data processors, each data processor comprising: first logic operable in a first clock domain and further logic operable in a second clock domain, said first and second clock domains being asynchronous with each other; a synchroniser operable to synchronise a signal processed by said first logic to produce a signal synchronised to said second clock domain; a synchronised signal output operable to export from said data processor said synchronised signal output from said synchroniser; and a signal input operable to import a signal to said data processor, said data processor being operable to route said imported signal to said further logic; wherein said plurality of data processors are arranged to operate in parallel with each other and said data processing apparatus further comprises: combining logic arranged to receive said exported synchronised signals from each of said plurality of data processors and to combine said exported synchronised signals to produce a resultant signal, said resultant signal being routed to each of said signal inputs of said plurality of data processors.

摘要翻译： 一种包括多个数据处理器的数据处理装置，每个数据处理器包括：可在第一时钟域中操作的第一逻辑和可在第二时钟域中操作的另外的逻辑，所述第一和第二时钟域彼此异步; 同步器，其可操作以使由所述第一逻辑处理的信号同步，以产生与所述第二时钟域同步的信号; 同步信号输出可操作以从所述数据处理器输出从所述同步器输出的所述同步信号; 以及可操作以将信号导入所述数据处理器的信号输入，所述数据处理器可操作以将所述导入的信号路由到所述另外的逻辑; 其中所述多个数据处理器被布置为彼此并行操作，并且所述数据处理装置还包括：组合逻辑，被布置为从所述多个数据处理器中的每一个接收所述输出的同步信号，并组合所述输出的同步信号以产生 所述结果信号被路由到所述多个数据处理器的每个所述信号输入端。

公开(公告)号：US20060271766A1

公开(公告)日：2006-11-30

申请号：US11138675

申请日：2005-05-27

申请人： Vladimir Vasekin ,  Andrew Rose ,  David Hart ,  Daniel Schostak

发明人： Vladimir Vasekin ,  Andrew Rose ,  David Hart ,  Daniel Schostak

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3838

摘要： Dynamic fetch rate control for a prefetch unit 4 fetching program instructions from a pipelined memory system 2 is provided. The prefetch unit receives a fetch rate control signal from a fetch rate controller 8. The fetch rate controller 8 is responsive to program instructions currently held within an instruction queue 6 to determine the fetch rate control signal to be generated.

摘要翻译： 提供了从流水线存储器系统2获取程序指令的预取单元4的动态获取速率控制。 预取单元从获取速率控制器8接收获取速率控制信号。 获取速率控制器8响应于当前保持在指令队列6内的程序指令来确定要生成的获取速率控制信号。

公开(公告)号：US20070255927A1

公开(公告)日：2007-11-01

申请号：US11414547

申请日：2006-05-01

申请人： Vladimir Vasekin ,  Andrew Rose ,  David Hart ,  Javed Osmany

发明人： Vladimir Vasekin ,  Andrew Rose ,  David Hart ,  Javed Osmany

IPC分类号： G06F9/34

CPC分类号： G06F9/383 ,  G06F9/342 ,  G06F9/3832 ,  G06F12/0215 ,  G06F12/0292 ,  G06F12/06

摘要： A data processing apparatus having a plurality of memories is provided in which address generation logic (109) outputs to at least one of the plurality of memories a target memory address corresponding to the data to be accessed. Target memory prediction logic (113) outputs a prediction indicating in which one of the plurality of memories a target data is stored. The target memory prediction logic (113) outputs the prediction in the same processing cycle as the output of the target memory address by the address generation logic (109). An associated method is also provided.

摘要翻译： 提供具有多个存储器的数据处理装置，其中地址生成逻辑（109）向多个存储器中的至少一个输出与要访问的数据相对应的目标存储器地址。 目标存储器预测逻辑（113）输出指示多个存储器中的哪个存储器存储目标数据的预测。 目标存储器预测逻辑（113）通过地址生成逻辑（109）在与目标存储器地址的输出相同的处理周期中输出预测。 还提供了相关联的方法。

公开(公告)号：US20050278508A1

公开(公告)日：2005-12-15

申请号：US11004227

申请日：2004-12-06

申请人： Vladimir Vasekin ,  Andrew Rose

发明人： Vladimir Vasekin ,  Andrew Rose

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3017 ,  G06F9/30178 ,  G06F9/3853 ,  G06F9/3885

摘要： A data processing system including an instruction cache 8 and an instruction decompression circuit 10 between the instruction cache 8 and a compressed instruction data memory 12. The instruction decompression circuit decompresses compressed instruction data CID recovered from the compressed instruction data memory and forms program instructions which are supplied to the instruction cache. The program instructions are compressed in blocks of program instructions with an associated mask value where the bit values within the mask indicate whether corresponding bit slices within the blocks of program instructions are to be represented by a default bit value or a separately specified by bit slice specifier values. This technique is particularly well suited to VLIW processors.

摘要翻译： 数据处理系统，包括在指令高速缓存8和压缩指令数据存储器12之间的指令高速缓存8和指令解压缩电路10。 指令解压缩电路解压缩从压缩指令数据存储器恢复的压缩指令数据CID，并形成提供给指令高速缓存的程序指令。 程序指令以具有关联掩码值的程序指令块压缩，其中掩码内的位值指示程序指令块内的相应位片是否由缺省位值表示，或由位片指定符单独指定 价值观。 这种技术特别适用于VLIW处理器。

公开(公告)号：US20050283593A1

公开(公告)日：2005-12-22

申请号：US10870548

申请日：2004-06-18

申请人： Vladimir Vasekin ,  Andrew Rose ,  Stuart Biles

发明人： Vladimir Vasekin ,  Andrew Rose ,  Stuart Biles

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3848

摘要： A branch prediction mechanism within a pipelined processing apparatus uses a history value HV which records preceding branch outcomes in either a first mode or a second mode. In the first mode respective bits within the history value represent a mixture of branch taken and branch not taken outcomes. In the second mode a count value within the history value indicates a count of a contiguous sequence of branch taken outcomes.

摘要翻译： 流水线处理装置内的分支预测机构使用历史值HV，其以第一模式或第二模式记录先前分支结果。 在第一个模式中，历史值中的各个位表示分支取和分支未采取结果的混合。 在第二模式中，历史值内的计数值表示分支采取结果的连续序列的计数。

公开(公告)号：US20050216711A1

公开(公告)日：2005-09-29

申请号：US10807498

申请日：2004-03-24

申请人： David Butcher ,  Stephen Hill ,  Hedley Francis ,  Vladimir Vasekin ,  Andrew Rose

发明人： David Butcher ,  Stephen Hill ,  Hedley Francis ,  Vladimir Vasekin ,  Andrew Rose

IPC分类号： G06F9/00 ,  G06F9/318 ,  G06F9/355 ,  G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/30174 ,  G06F9/355

摘要： A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.

摘要翻译： 处理器6设置有指令解码器18，该指令解码器18响应于存储器访问指令来确定正在使用的基本寄存器值是否与空值匹配，并且如果发生这样的匹配，则分支到空值异常处理程序。

公开(公告)号：US20050066131A1

公开(公告)日：2005-03-24

申请号：US10668373

申请日：2003-09-24

申请人： Stuart Biles ,  Christopher Dornan ,  Vladimir Vasekin ,  Andrew Rose

发明人： Stuart Biles ,  Christopher Dornan ,  Vladimir Vasekin ,  Andrew Rose

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/023 ,  G06F9/30043 ,  G06F9/383

摘要： An apparatus and method for loading data values from a memory system are provided. The data processing apparatus comprises a data processing unit operable to execute instructions, and a register file having a plurality of registers operable to store data values accessible by the data processing unit when executing the instructions. Further, a holding register is provided which does not form one of a working set of registers of the register file, and is operable to temporarily store a data value, the holding register having a data portion for storing the data value, and an identifier portion operable to store identifier data associated with the data value. The data processing unit is then responsive to a preload instruction to issue a preload memory access request to a memory system to cause a data value identified by the preload instruction to be located in the memory system, and dependent on predetermined criteria to cause a copy of that data value along with associated identifier data to be loaded from the memory system into the holding register. Furthermore, the data processing unit is responsive to a load instruction to cause a comparison operation to be performed to determine whether identifier data derived from the load instruction matches the identifier data in the identifier portion of the holding register. If it does, the data value stored in the holding register is made available to the data processing unit without requiring a memory access request to be issued to the memory system. Only in the event of there being no match does the memory access request get issued to the memory system to cause a data value identified by the load instruction to be made available to the data processing unit from the memory system.

摘要翻译： 提供了一种用于从存储器系统加载数据值的装置和方法。 数据处理装置包括可操作以执行指令的数据处理单元和具有多个寄存器的寄存器文件，其可操作以在执行指令时存储由数据处理单元可访问的数据值。 此外，提供一个保持寄存器，其不形成寄存器堆的寄存器的工作组之一，并且可操作以临时存储数据值，具有用于存储数据值的数据部分的保持寄存器和标识符部分 可操作地存储与数据值相关联的标识符数据。 数据处理单元然后响应于预加载指令向存储器系统发出预加载存储器访问请求，以使得由预加载指令识别的数据值位于存储器系统中，并且依赖于预定标准，以使得 该数据值以及要从存储器系统加载到保持寄存器中的相关联的标识符数据。 此外，数据处理单元响应于加载指令以执行比较操作，以确定从加载指令导出的标识符数据是否与保持寄存器的标识符部分中的标识符数据匹配。 如果是这样，则保存寄存器中存储的数据值可用于数据处理单元，而不需要向存储器系统发出存储器访问请求。 只有在没有匹配的情况下，存储器访问请求被发送到存储器系统才能使由加载指令识别的数据值从存储器系统提供给数据处理单元。

公开(公告)号：US20070208924A1

公开(公告)日：2007-09-06

申请号：US11632698

申请日：2004-07-27

申请人： Simon Ford ,  Andrew Rose

发明人： Simon Ford ,  Andrew Rose

IPC分类号： G06F9/30

CPC分类号： G06F9/30072 ,  G06F9/3001 ,  G06F9/30163

摘要： A data processing apparatus and method of handling conditional instructions in such a data processing apparatus are provided. The data processing apparatus has a pipelined processing unit for executing instructions including at least one conditional instruction from a set of conditional instructions, and a register file having a plurality of registers operable to store data values for access by the pipelined processing unit when executing the instructions. A register specified by an instruction may be either a source register holding a source data value for that instruction or a destination register into which is stored a result data value generated by execution of that instruction. The register file has a predetermined number of read ports via which data values can be read from registers of the register file. The pipelined processing unit is operable when executing the at least one conditional instruction to produce a result data value which, dependent on the existence of the condition specified by that conditional instruction, represents either the result of the computation specified by that conditional instruction or a current data value stored in the destination register for that conditional instruction. Further, each conditional instruction in the set is constrained to specify a register that is both a source register and a destination register for that conditional instruction, thereby reducing the minimum number of read ports required to support execution of that conditional instruction by the pipelined processing unit.

摘要翻译： 提供了一种在这种数据处理装置中处理条件指令的数据处理装置和方法。 数据处理装置具有流水线处理单元，用于执行包括来自一组条件指令的至少一个条件指令的指令，以及具有多个寄存器的寄存器文件，该多个寄存器可操作以在执行指令时存储由流水线处理单元进行访问的数据值 。 由指令指定的寄存器可以是保存该指令的源数据值的源寄存器或存储通过执行该指令而生成的结果数据值的目标寄存器。 寄存器文件具有预定数量的读取端口，经由该读取端口可以从寄存器文件的寄存器读取数据值。 流水线处理单元在执行至少一个条件指令以产生结果数据值时可操作，该结果数据值取决于由该条件指令指定的条件的存在表示由该条件指令指定的计算结果或当前值 存储在该条件指令的目标寄存器中的数据值。 此外，集合中的每个条件指令被限制为指定用于该条件指令的源寄存器和目的地寄存器的寄存器，由此减少支持由流水线处理单元执行该条件指令所需的读端口的最小数量 。

公开(公告)号：US20050125641A1

公开(公告)日：2005-06-09

申请号：US10889367

申请日：2004-07-13

申请人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

发明人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/00

CPC分类号： G06F9/30167 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30145

摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.

摘要翻译： 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以对在至少一个寄存器中访问的多个数据元素并行地执行数据处理操作。 访问逻辑可操作以响应于单个访问指令来移动指定寄存器之间的多个数据元素和其中数据元素被存储为具有结构格式的结构的阵列的连续存储块，所述结构格式具有多个 组件。 单个访问指令标识结构格式的组件的数量，并且访问逻辑还可用于在移动多个数据元素时重新排列多个数据元素，使得每个指定的寄存器存储一个组件的数据元素，而在存储器中数据元素是 存储为结构数组。

公开(公告)号：US20050125636A1

公开(公告)日：2005-06-09

申请号：US10889316

申请日：2004-07-13

申请人： Simon Ford ,  Dominic Symes ,  Daniel Kershaw ,  Andrew Rose

发明人： Simon Ford ,  Dominic Symes ,  Daniel Kershaw ,  Andrew Rose

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/315 ,  G06F15/00 ,  G06F15/80 ,  G06F17/16

CPC分类号： G06F9/3013 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3887

摘要： A data processing apparatus is disclosed. The apparatus comprises a register data store comprising a plurality of registers. The apparatus further comprises a data processor operable to perform in parallel a data processing operation on data elements; and decode logic responsive to a single vector-by-scalar instruction to control the data processor so as to specify one of the plurality of registers as a first source register operable to store a plurality of source data elements, to specify another of the plurality of registers as a second source register operable to store a plurality of selectable data elements, to select one of said selectable data elements as a scalar operand and to perform a vector-by-scalar operation in parallel on the source data elements, each vector-by-scalar operation causing a resultant data element to be generated from a source data element and the scalar operand. By providing a source register which contains selectable data elements it is possible to select one of those data elements as a scalar operand and to perform multiple vector-by-scalar operations in parallel using the same scalar operand on all source data elements.

摘要翻译： 公开了一种数据处理装置。 该装置包括一个包括多个寄存器的寄存器数据存储器。 该装置还包括数据处理器，可操作以并行地执行数据元素的数据处理操作; 以及响应于单个逐标量指令来解码逻辑以控制所述数据处理器，以便将所述多个寄存器中的一个指定为可操作以存储多个源数据元素的第一源寄存器，以指定所述多个 寄存器作为可操作以存储多个可选择数据元素的第二源寄存器，将所述可选数据元素中的一个选择为标量操作数，并且对源数据元素并行执行逐标量运算，每个向量 - 标量操作，使得从源数据元素和标量操作数生成结果数据元素。 通过提供包含可选数据元素的源寄存器，可以选择这些数据元素中的一个作为标量操作数，并且使用所有源数据元素上的相同标量操作数并行地执行多个逐标量操作。