公开(公告)号：US20220365135A1

公开(公告)日：2022-11-17

申请号：US17320165

申请日：2021-05-13

Applicant: Apple Inc.

Inventor： Fabien S. Faure ,  Arnaud J. Forestier ,  Vikram Mehta

IPC: G01R31/3177 ,  G01R31/317

Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

公开(公告)号：US20230384377A1

公开(公告)日：2023-11-30

申请号：US18303401

申请日：2023-04-19

Applicant: Apple Inc.

Inventor： Fabien S. Faure ,  Arnaud J. Forestier ,  Vikram Mehta

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/319 ,  G01R31/3185 ,  G01R31/66 ,  G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/31725 ,  G01R31/31713 ,  G01R31/31716 ,  G01R31/31926 ,  G01R31/318572 ,  G01R31/31723 ,  G01R31/31712 ,  G01R31/31715 ,  G01R31/66 ,  G01R31/2889

Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

公开(公告)号：US11899061B2

公开(公告)日：2024-02-13

申请号：US17347284

申请日：2021-06-14

Applicant: Apple Inc.

Inventor： Fabien S. Faure ,  Si Chen ,  Mansour Keramat ,  Arnaud J. Forestier

IPC: G08B21/00 ,  G01R31/317 ,  H03M1/12 ,  G01R13/02 ,  G06F11/10 ,  G01R19/25

CPC classification number: G01R31/31713 ,  G01R13/029 ,  G01R13/0272 ,  G01R19/2503 ,  G01R31/31705 ,  G06F11/10 ,  H03M1/12

Abstract: A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.

公开(公告)号：US20220397604A1

公开(公告)日：2022-12-15

申请号：US17347284

申请日：2021-06-14

Applicant: Apple Inc.

Inventor： Fabien S. Faure ,  Si Chen ,  Mansour Keramat ,  Arnaud J. Forestier

IPC: G01R31/317 ,  H03M1/12 ,  G01R13/02 ,  G01R19/25 ,  G06F11/10

Abstract: A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.

公开(公告)号：US11662380B2

公开(公告)日：2023-05-30

申请号：US17320165

申请日：2021-05-13

Applicant: Apple Inc.

Inventor： Fabien S. Faure ,  Arnaud J. Forestier ,  Vikram Mehta

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G01R31/28 ,  G01R31/66

CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/31725 ,  G01R31/2889 ,  G01R31/31712 ,  G01R31/31715 ,  G01R31/31716 ,  G01R31/31723 ,  G01R31/31926 ,  G01R31/318572 ,  G01R31/66

Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

公开(公告)号：US11940491B2

公开(公告)日：2024-03-26

申请号：US18303401

申请日：2023-04-19

Applicant: Apple Inc.

Inventor： Fabien S. Faure ,  Arnaud J. Forestier ,  Vikram Mehta

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G01R31/66

CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/31725 ,  G01R31/2889 ,  G01R31/31712 ,  G01R31/31715 ,  G01R31/31716 ,  G01R31/31723 ,  G01R31/318572 ,  G01R31/31926 ,  G01R31/66

Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.