-
公开(公告)号：US11940491B2
公开(公告)日：2024-03-26
申请号：US18303401
申请日：2023-04-19
Applicant: Apple Inc.
Inventor： Fabien S. Faure , Arnaud J. Forestier , Vikram Mehta
IPC: G01R31/3177 , G01R31/317 , G01R31/28 , G01R31/3185 , G01R31/319 , G01R31/66
CPC classification number: G01R31/3177 , G01R31/31713 , G01R31/31725 , G01R31/2889 , G01R31/31712 , G01R31/31715 , G01R31/31716 , G01R31/31723 , G01R31/318572 , G01R31/31926 , G01R31/66
Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.
-
公开(公告)号：US20230384377A1
公开(公告)日：2023-11-30
申请号：US18303401
申请日：2023-04-19
Applicant: Apple Inc.
Inventor： Fabien S. Faure , Arnaud J. Forestier , Vikram Mehta
IPC: G01R31/3177 , G01R31/317 , G01R31/319 , G01R31/3185 , G01R31/66 , G01R31/28
CPC classification number: G01R31/3177 , G01R31/31725 , G01R31/31713 , G01R31/31716 , G01R31/31926 , G01R31/318572 , G01R31/31723 , G01R31/31712 , G01R31/31715 , G01R31/66 , G01R31/2889
Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.
-
公开(公告)号：US10242723B1
公开(公告)日：2019-03-26
申请号：US15846992
申请日：2017-12-19
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Fabien S. Faure
Abstract: A method and apparatus for performing a background calibration in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller is coupled to receive data during reads from the memory on a functional data path and a duplicate data path. The memory controller further includes calibration circuitry. During reads of data conducted during normal operation, the calibration circuit calibrates a first delay locked loop (DLL) in the duplicate data path. A second DLL, in the functional data path, may be adjusted based on the calibrations conducted in the duplicate data path.
-
公开(公告)号：US20180074743A1
公开(公告)日：2018-03-15
申请号：US15263833
申请日：2016-09-13
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Liang Deng , Kai Lun Hsiung , Manu Gulati , Rakesh L. Notani , Sukalpa Biswas , Venkata Ramana Malladi , Gregory S. Mathews , Enming Zheng , Fabien S. Faure
CPC classification number: G06F3/0634 , G06F1/08 , G06F1/324 , G06F3/0625 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F3/0683 , G06F13/1689 , G06F13/4243 , Y02D10/14 , Y02D10/151
Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.
-
公开(公告)号：US11899061B2
公开(公告)日：2024-02-13
申请号：US17347284
申请日：2021-06-14
Applicant: Apple Inc.
Inventor： Fabien S. Faure , Si Chen , Mansour Keramat , Arnaud J. Forestier
CPC classification number: G01R31/31713 , G01R13/029 , G01R13/0272 , G01R19/2503 , G01R31/31705 , G06F11/10 , H03M1/12
Abstract: A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.
-
Patent Agency Ranking
公开(公告)号：US20220397604A1
公开(公告)日：2022-12-15
申请号：US17347284
申请日：2021-06-14
Applicant: Apple Inc.
Inventor： Fabien S. Faure , Si Chen , Mansour Keramat , Arnaud J. Forestier
IPC: G01R31/317 , H03M1/12 , G01R13/02 , G01R19/25 , G06F11/10
Abstract: A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.
-
公开(公告)号：US09990973B1
公开(公告)日：2018-06-05
申请号：US15436212
申请日：2017-02-17
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Fabien S. Faure
IPC: G11C7/22
CPC classification number: G06F13/42 , G11C2207/2254
Abstract: A method and apparatus for using neighboring sampling points in a memory subsystem calibration is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto. A calibration unit in the memory controller is configured to perform calibrations of a data strobe signal and a reference voltage to determine eye openings for signals conveyed between the memory and the memory controller. Performing the calibration includes determining a number of different calibration points and computing initial scores for each of the calibration points. The method further includes calculating adjusted scores for each calibration point. For a given calibration point, the adjusted score includes weighted values of one or more calibration points that are adjacent thereto. The method further includes selecting a calibration point having the highest adjusted score as the calibrated value.
-
公开(公告)号：US11662380B2
公开(公告)日：2023-05-30
申请号：US17320165
申请日：2021-05-13
Applicant: Apple Inc.
Inventor： Fabien S. Faure , Arnaud J. Forestier , Vikram Mehta
IPC: G01R31/3177 , G01R31/317 , G01R31/3185 , G01R31/319 , G01R31/28 , G01R31/66
CPC classification number: G01R31/3177 , G01R31/31713 , G01R31/31725 , G01R31/2889 , G01R31/31712 , G01R31/31715 , G01R31/31716 , G01R31/31723 , G01R31/31926 , G01R31/318572 , G01R31/66
Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.
-
公开(公告)号：US10408863B2
公开(公告)日：2019-09-10
申请号：US15848804
申请日：2017-12-20
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Fabien S. Faure , Rakesh L. Notani
IPC: G11C7/10 , G01R19/165 , G11C5/14 , G11C8/12 , G11C5/02
Abstract: A method and apparatus for predicting a reference voltage in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller includes a lookup table having a number of different reference voltage values each corresponding to one of a number of different performance states. The memory controller further includes calibration circuitry configured to determine reference voltages for operation in various performance states. Responsive to returning to a performance state after operating in another, the calibration circuitry may restore the reference voltage to its most recently used value, and also obtain a predicted reference voltage. Calibrations may be performed at both the restored reference voltage and the predicted reference voltage obtained from the lookup table. The subsequent operating reference voltage may then be selected based on which of the two calibrations resulted in the largest data eye width.
-
公开(公告)号：US10175905B2
公开(公告)日：2019-01-08
申请号：US15263833
申请日：2016-09-13
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Liang Deng , Kai Lun Hsiung , Manu Gulati , Rakesh L. Notani , Sukalpa Biswas , Venkata Ramana Malladi , Gregory S. Mathews , Enming Zheng , Fabien S. Faure
Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.014 seconds)
