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公开(公告)号:US20240395686A1
公开(公告)日:2024-11-28
申请号:US18324612
申请日:2023-05-26
Applicant: Apple Inc.
Inventor: Wei Chen , Jie-Hua Zhao , Jun Zhai , Kunzhong Hu , Arun Sasi , Balaji Nandhivaram Muthuraman , Zezhou Liu
IPC: H01L23/498 , H01L23/00 , H01L23/538
Abstract: Electronic packages and electronic systems are described in which a package redistribution layer of the electronic package includes structural features such a via line connections to reduce stress concentration, particularly when the package redistribution layer is formed of organic dielectric materials.
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公开(公告)号:US20240249989A1
公开(公告)日:2024-07-25
申请号:US18158090
申请日:2023-01-23
Applicant: Apple Inc.
Inventor: Wei Chen , Balaji Nandhivaram Muthuraman , Arun Sasi , Jie-Hua Zhao , Suk-Kyu Ryu , Jun Zhai , Dominic Morache , Young Doo Jeon
CPC classification number: H01L23/3157 , H01L23/34 , H01L24/16 , H01L24/17 , H01L2224/16113 , H01L2224/16225 , H01L2224/17055 , H01L2924/10162 , H01L2924/1811 , H01L2924/182
Abstract: Microelectronic structures with selectively applied underfill material and/or edge bond material are described. In an embodiment, isolated underfill regions and/or edge bond regions are applied to adjacent to one or more edges of an electronic device and form a plurality of vent openings along the one or more edges.
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