公开(公告)号：US11545455B2

公开(公告)日：2023-01-03

申请号：US16423931

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US09548288B1

公开(公告)日：2017-01-17

申请号：US14966482

申请日：2015-12-11

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Chonghua Zhong ,  Shawn Searles ,  Jun Zhai ,  Young Doo Jeon ,  Huabo Chen

IPC: H01L25/16 ,  H01L23/528 ,  H01L23/50 ,  H01L21/78 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/16 ,  H01L21/768 ,  H01L21/78 ,  H01L23/50 ,  H01L23/528 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16265 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/145 ,  H01L2924/14511 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2224/81

Abstract: A system that includes an integrated circuit die and a power supply decoupling unit is disclosed. The system includes an integrated circuit die, and interconnection region, and a decoupling unit. The integrated circuit die includes a plurality of circuits, which each include multiple devices interconnected using wires fabricated on a first plurality of conductive layers. The interconnection region includes multiple solder balls, and multiple conductive paths, each of which includes wires fabricated on a second plurality conductive layers. At least one solder ball is connected to an Input/Output terminal of a first circuit of the plurality of circuits via one of the conductive paths. The decoupling unit may include a plurality of capacitors and a plurality of terminals. Each terminal of the decoupling unit may be coupled to a respective power terminal of a second circuit of the plurality of circuits via the conductive paths.

Abstract translation: 公开了一种包括集成电路管芯和电源去耦单元的系统。 该系统包括集成电路管芯和互连区域以及去耦单元。 集成电路管芯包括多个电路，每个电路包括使用在第一多个导电层上制造的导线互连的多个器件。 互连区域包括多个焊球，以及多个导电路径，每个导电路径包括制造在第二多个导电层上的导线。 至少一个焊球通过导电路径之一连接到多个电路中的第一电路的输入/输出端子。 去耦单元可以包括多个电容器和多个端子。 去耦单元的每个端子可以经由导电路径耦合到多个电路中的第二电路的相应电源端子。

公开(公告)号：US20240421126A1

公开(公告)日：2024-12-19

申请号：US18598938

申请日：2024-03-07

Applicant: Apple Inc.

Inventor： Chi Nung Ni ,  Wei Chen ,  Weiming Chris Chen ,  Vidhya Ramachandran ,  Jie-Hua Zhao ,  Suk-Kyu Ryu ,  Myung Jin Yim ,  Chih-Ming Chung ,  Jun Zhai ,  Young Doo Jeon ,  Seungjae Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/58 ,  H01L29/06

Abstract: Integrated circuit (IC) structures, electronic modules, and methods of fabrication are described in which direct bonded interfaces are removed at corners or edges to counteract the potential for non-bonding or delamination. This can be accomplished during singulation, in which a side recess is formed through an entire thickness of an electronic component and into a direct bonded die, followed by final singulation of the IC structure.

公开(公告)号：US20240249989A1

公开(公告)日：2024-07-25

申请号：US18158090

申请日：2023-01-23

Applicant: Apple Inc.

Inventor： Wei Chen ,  Balaji Nandhivaram Muthuraman ,  Arun Sasi ,  Jie-Hua Zhao ,  Suk-Kyu Ryu ,  Jun Zhai ,  Dominic Morache ,  Young Doo Jeon

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/34

CPC classification number: H01L23/3157 ,  H01L23/34 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/17055 ,  H01L2924/10162 ,  H01L2924/1811 ,  H01L2924/182

Abstract: Microelectronic structures with selectively applied underfill material and/or edge bond material are described. In an embodiment, isolated underfill regions and/or edge bond regions are applied to adjacent to one or more edges of an electronic device and form a plurality of vent openings along the one or more edges.

公开(公告)号：US11908819B2

公开(公告)日：2024-02-20

申请号：US18046134

申请日：2022-10-12

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/498 ,  H01L24/11 ,  H01L24/13 ,  H01L24/25 ,  H01L24/26 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/11003 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14517 ,  H01L2224/16112 ,  H01L2224/24996 ,  H01L2224/2501 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/73204 ,  H01L2224/83051

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US20200381383A1

公开(公告)日：2020-12-03

申请号：US16423931

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US20240421013A1

公开(公告)日：2024-12-19

申请号：US18585834

申请日：2024-02-23

Applicant: Apple Inc.

Inventor： Jixuan Gong ,  Vidhya Ramachandran ,  Jie-Hua Zhao ,  Young Doo Jeon ,  Wei Chen ,  Jun Zhai

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/58

Abstract: Integrated circuit (IC) structure, IC die structures and methods of fabrication are described in which one or more edge recesses are formed in an IC die. Upon direct bonding to an electronic component, a molding compound can be applied to the bonded structure where the molding compound fills the one or more edge recesses and encroached underneath the IC die and between the IC die and the electronic component.

公开(公告)号：US20230245988A1

公开(公告)日：2023-08-03

申请号：US18058006

申请日：2022-11-22

Applicant: Apple Inc.

Inventor： Kwan-Yu Lai ,  Kunzhong Hu ,  Jun Zhai ,  Young Doo Jeon

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/73 ,  H01L24/13 ,  H01L24/20 ,  H01L24/19 ,  H01L24/14 ,  H01L2224/73101 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/19 ,  H01L2224/11002 ,  H01L2224/11916 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/1184 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13018 ,  H01L2224/13075 ,  H01L2224/13541 ,  H01L2224/13552 ,  H01L2224/13575 ,  H01L2924/35121

Abstract: Die reconstitution methods and dies with reconstituted contact bumps are described. In an embodiment, a die reconstitution method includes reconstituting a plurality of dies including first contact bumps of a first type, partially removing the first contact bumps, and forming second contact bumps of a second type on top of the partially removed first contact bumps, where the second type is different than the first type.

公开(公告)号：US20230115986A1

公开(公告)日：2023-04-13

申请号：US18046134

申请日：2022-10-12

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.