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公开(公告)号：US20170286290A1
公开(公告)日：2017-10-05
申请号：US15630376
申请日：2017-06-22
Applicant: Apple Inc.
Inventor： Daniel J. Post , Nir Jacob Wakrat
CPC classification number: G06F12/0246 , G06F3/061 , G06F3/0613 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/068 , G06F12/1408 , G06F13/1673 , G06F21/71 , G06F21/79 , G06F2212/1052 , Y02D10/14
Abstract: Systems and methods are disclosed for efficient buffering for a system having non-volatile memory (“NVM”). In some embodiments, a control circuitry of a system can use heuristics to determine whether to perform buffering of one or more write commands received from a file system. In other embodiments, the control circuitry can minimize read energy and buffering overhead by efficiently re-ordering write commands in a queue along page-aligned boundaries of a buffer. In further embodiments, the control circuitry can optimally combine write commands from a buffer with write commands from a queue. After combining the commands, the control circuitry can dispatch the commands in a single transaction.
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公开(公告)号：US09690953B2
公开(公告)日：2017-06-27
申请号：US14212049
申请日：2014-03-14
Applicant: Apple Inc.
Inventor： Andrew W. Vogan , Matthew J. Byom , Alexander C. Sanks , Daniel J. Post , Hari Hara Kumar Maharaj , Nir Jacob Wakrat , Kenneth L. Herman
CPC classification number: G06F21/79 , G06F2221/2107
Abstract: Systems and methods are disclosed for generating efficient reads for a system having non-volatile memory (“NVM”). A read command can be separated by a host processor of the system into two phases: a) transmitting a command to a storage processor of the system, where the command is associated with one or more logical addresses, and b) generating data transfer information. The host processor can generate the data transfer information while the storage processor is processing the command from the host processor. Once the data transfer information has been generated and data has been read from the NVM, the data can be transferred.
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公开(公告)号：US09477596B2
公开(公告)日：2016-10-25
申请号：US14754433
申请日：2015-06-29
Applicant: Apple Inc.
Inventor： Daniel J. Post , Nir Jacob Wakrat , Vadim Khmelnitsky
IPC: G06F12/02
CPC classification number: G06F12/0253 , G06F12/0238 , G06F12/0246 , G06F2212/1024 , G06F2212/1044 , G06F2212/7201 , G06F2212/7205 , G06F2212/7209
Abstract: Systems and methods are disclosed for logical block address (“LBA) bitmap usage for a system having non-volatile memory (“NVM”). A bitmap can be stored in volatile memory of the system, where the bitmap can store the mapping statuses of one or more logical addresses. By using the bitmap, the system can determine the mapping status of a LBA without having to access the NVM. In addition, the system can update the mapping status of a LBA with minimal NVM accesses. By reducing the number of NVM accesses, the system can avoid triggering a garbage collection process, which can improve overall system performance.
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公开(公告)号：US20150301938A1
公开(公告)日：2015-10-22
申请号：US14754433
申请日：2015-06-29
Applicant: Apple Inc.
Inventor： Daniel J. Post , Nir Jacob Wakrat , Vadim Khmelnitsky
IPC: G06F12/02
CPC classification number: G06F12/0253 , G06F12/0238 , G06F12/0246 , G06F2212/1024 , G06F2212/1044 , G06F2212/7201 , G06F2212/7205 , G06F2212/7209
Abstract: Systems and methods are disclosed for logical block address (“LBA) bitmap usage for a system having non-volatile memory (“NVM”). A bitmap can be stored in volatile memory of the system, where the bitmap can store the mapping statuses of one or more logical addresses. By using the bitmap, the system can determine the mapping status of a LBA without having to access the NVM. In addition, the system can update the mapping status of a LBA with minimal NVM accesses. By reducing the number of NVM accesses, the system can avoid triggering a garbage collection process, which can improve overall system performance.
Abstract translation: 公开了用于具有非易失性存储器（“NVM”）的系统的逻辑块地址（“LBA”）位图使用的系统和方法。 位图可以存储在系统的易失性存储器中，其中位图可以存储一个或多个逻辑地址的映射状态。 通过使用位图，系统可以确定LBA的映射状态，而无需访问NVM。 此外，系统可以使用最小的NVM访问来更新LBA的映射状态。 通过减少NVM访问次数，系统可以避免触发垃圾收集过程，从而提高整体系统性能。
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公开(公告)号：US20150227460A1
公开(公告)日：2015-08-13
申请号：US14693260
申请日：2015-04-22
Applicant: APPLE INC.
Inventor： Daniel J. Post , Nir J. Wakrat
CPC classification number: G06F12/0246 , G06F3/061 , G06F3/0613 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/068 , G06F12/1408 , G06F13/1673 , G06F21/71 , G06F21/79 , G06F2212/1052 , Y02D10/14
Abstract: Systems and methods are disclosed for efficient buffering for a system having non-volatile memory (“NVM”). In some embodiments, a control circuitry of a system can use heuristics to determine whether to perform buffering of one or more write commands received from a file system. In other embodiments, the control circuitry can minimize read energy and buffering overhead by efficiently re-ordering write commands in a queue along page-aligned boundaries of a buffer. In further embodiments, the control circuitry can optimally combine write commands from a buffer with write commands from a queue. After combining the commands, the control circuitry can dispatch the commands in a single transaction.
Abstract translation: 公开了用于具有非易失性存储器（“NVM”）的系统的有效缓冲的系统和方法。 在一些实施例中，系统的控制电路可以使用启发式方法来确定是否执行从文件系统接收的一个或多个写入命令的缓冲。 在其他实施例中，控制电路可以通过在缓冲器的页对准边界中有效地重新排序队列中的写入命令来最小化读取能量和缓冲开销。 在另外的实施例中，控制电路可以最佳地组合来自缓冲器的写入命令与来自队列的写入命令。 在组合命令之后，控制电路可以在单个事务中分派命令。
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Patent Agency Ranking
公开(公告)号：US20140143634A1
公开(公告)日：2014-05-22
申请号：US14166174
申请日：2014-01-28
Applicant: Apple Inc.
Inventor： Daniel J. Post
IPC: G06F11/10
CPC classification number: G06F11/1068
Abstract: This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword.
Abstract translation: 这可以涉及非易失性存储器（“NVM”）的非正规奇偶校验分配，例如闪速存储器，以及通过元数据标签检测非常规奇偶校验。 例如，NVM的每个码字可以包括可以通过NVM随机分布的一个或多个奇偶校验页。 为了将页面标识为奇偶校验页，奇偶校验页标记可以包含在该页的元数据中。 在NVM上电期间，可以创建包括页面的逻辑到物理地址映射的地址表。 但是，在创建此地址表时可以跳过包含奇偶校验页标记的页面。 另外，通过具有与码字相关联的两个或多个奇偶校验页，可以提供附加的保护层来修复该码字中的错误。
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公开(公告)号：US09703700B2
公开(公告)日：2017-07-11
申请号：US14693260
申请日：2015-04-22
Applicant: APPLE INC.
Inventor： Daniel J. Post , Nir J. Wakrat
CPC classification number: G06F12/0246 , G06F3/061 , G06F3/0613 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/068 , G06F12/1408 , G06F13/1673 , G06F21/71 , G06F21/79 , G06F2212/1052 , Y02D10/14
Abstract: Systems and methods are disclosed for efficient buffering for a system having non-volatile memory (“NVM”). In some embodiments, a control circuitry of a system can use heuristics to determine whether to perform buffering of one or more write commands received from a file system. In other embodiments, the control circuitry can minimize read energy and buffering overhead by efficiently re-ordering write commands in a queue along page-aligned boundaries of a buffer. In further embodiments, the control circuitry can optimally combine write commands from a buffer with write commands from a queue. After combining the commands, the control circuitry can dispatch the commands in a single transaction.
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公开(公告)号：US09361036B2
公开(公告)日：2016-06-07
申请号：US14754468
申请日：2015-06-29
Applicant: Apple Inc.
Inventor： Andrew W. Vogan , Daniel J. Post
CPC classification number: G06F3/0619 , G06F3/0631 , G06F3/0679 , G06F11/1004 , G06F11/1008 , G06F11/1048
Abstract: Systems and methods are disclosed for correcting block errors. In particular, a system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This enables a space efficient approach for recovering from single-block data errors.
Abstract translation: 公开了用于校正块错误的系统和方法。 特别地，系统可以每页模数地存储奇偶校验页，其中可以将NVM的块或带的预定数量的页分配为页模XOR（“PMX”）奇偶页。 这实现了从单块数据错误中恢复的空间有效的方法。
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9.发明申请公开(公告)号：US20150301760A1
公开(公告)日：2015-10-22
申请号：US14754468
申请日：2015-06-29
Applicant: Apple Inc.
Inventor： Andrew W. Vogan , Daniel J. Post
CPC classification number: G06F3/0619 , G06F3/0631 , G06F3/0679 , G06F11/1004 , G06F11/1008 , G06F11/1048
Abstract: Systems and methods are disclosed for correction of block errors for a system having non-volatile memory (“NVM”). In particular, the system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts.
Abstract translation: 公开了用于校正具有非易失性存储器（“NVM”）的系统的块错误的系统和方法。 特别地，系统可以每页模数地存储奇偶校验页，其中可以将NVM的块或带的预定数量的页分配为页模XOR（“PMX”）奇偶校验页。 这可以是用于从单块数据错误（例如，单页不可校正纠错码（“uECC”））和/或由字线短路引起的错误进行恢复的空间有效的方法。
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公开(公告)号：US08990614B2
公开(公告)日：2015-03-24
申请号：US13829692
申请日：2013-03-14
Applicant: Apple Inc.
Inventor： Andrew W. Vogan , Daniel J. Post
CPC classification number: G06F11/1666 , G06F11/073 , G06F11/1068 , G06F12/0246 , G11C29/808 , G11C29/82
Abstract: Systems and methods are disclosed for improving performance of a system having non-volatile memory (“NVM”). The system can vertically re-vector defective blocks of a user region of the NVM to other blocks having the same plane or die's plane (“DIP”) but corresponding to a dead region of the NVM. Then, the system can select any band with more than one defective block and vertically re-vector one of its defective blocks to a band that has no defective blocks. At run-time, the system can monitor the number of vertical re-vectors per DIP. If at least one vertical re-vector has been performed on all DIPs of the NVM, a band of the user region can be allocated for the dead region.
Abstract translation: 公开了用于改善具有非易失性存储器（“NVM”）的系统的性能的系统和方法。 该系统可以垂直地将NVM的用户区域的缺陷块重新向量到具有相同平面或管芯平面（“DIP”）但对应于NVM的死区的其他块。 然后，系统可以选择具有多于一个缺陷块的任何频带，并将其缺陷块中的一个垂直重新矢量到没有有缺陷块的频带。 在运行时，系统可以监控每个DIP的垂直重新向量的数量。 如果在NVM的所有DIP上执行了至少一个垂直重新向量，则可以为死区分配用户区域的频带。
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