公开(公告)号：US20240273666A1

公开(公告)日：2024-08-15

申请号：US18450910

申请日：2023-08-16

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  David A. Gotwalt ,  Pratik Chandresh Shah ,  Jackson Dsouza ,  Subodh Asthana ,  Jairaj Dave ,  Piotr A. Dittrich ,  David E. Roberts

IPC: G06T1/20 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/485 ,  G06F9/4881

Abstract: Disclosed techniques relate to scheduling sets of graphics work using queues. In some embodiments, tracking circuitry implements entries for multiple tracking slots for a graphics processor. Queue access circuitry may access a data structure in memory that specifies multiple queues, where each queue enqueues control information for multiple sets of graphics work. Queue select circuitry may select sets of graphics work from the data structure based on one or more selection parameters and store control information for selected sets of graphics work in tracking slots of the tracking slot circuitry. Distribution circuitry may assign portions of respective sets of graphics work from the tracking slots to graphics processor circuitry for execution.

公开(公告)号：US11243598B2

公开(公告)日：2022-02-08

申请号：US16426633

申请日：2019-05-30

Applicant: Apple Inc.

Inventor： Tatsuya Iwamoto ,  Jason P. Jane ,  Rohan Sanjeev Patil ,  Kutty Banerjee ,  Subodh Asthana ,  Kyle J. Haughey

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06T1/20 ,  G06F17/18 ,  G06F1/3228

Abstract: Systems, methods, and computer readable media to manage power for a graphics processor are described. When the power management component determines the graphics processor is idle when processing a current frame by the graphics processor, the power management component predicts an idle period for the graphics processor based on the work history. The power management component obtains a first latency value indicative of a power on time period and a second latency value indicative of a power off time period for a graphics processor component, such as graphics processor hardware. The power management component provides power instructions to transition the graphics processor component to the power off state based on a determination that a combined latency value of the first latency value and the second latency value is less than the idle period.

公开(公告)号：US11055812B1

公开(公告)日：2021-07-06

申请号：US16883114

申请日：2020-05-26

Applicant: Apple Inc.

Inventor： Subodh Asthana

IPC: G06T1/20

Abstract: A method comprises obtaining a first plurality of render commands comprising at least a geometry stage and a fragment stage. An identification may be made as to which of the geometry stages of the first plurality of render commands are idempotent. Dependency information is determined for the first plurality of render commands, e.g., identifying and labeling both “true” and “artificial” dependencies between the stages of the commands. The first plurality of render commands may be encoded and executed by a graphics processing unit (GPU) according to a labeled execution graph generated based on the dependency information. During execution, the GPU may attempt to “opportunistically” launch at least one identified idempotent geometry stage command for which at least one artificial barrier still remains. If the opportunistically-launched geometry stage work fails, the work may be discarded, and the method may wait until all barriers have been met before attempting to relaunch it.