公开(公告)号：US20240070365A1

公开(公告)日：2024-02-29

申请号：US17823644

申请日：2022-08-31

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Antonietta Oliva

IPC: G06F30/392 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394

Abstract: A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout utilizes an isolation gate structure to provide routing between a signal input of an active gate and a backside metal layer. The isolation gate structure includes a metal fill surrounded by gate spacers. The metal fill connects between the topside layers in the device and the backside layer in the device. The metal fill may be connected to the signal input of the active gate through routing either in a topside metal layer or a metal wire placed in a topside insulating layer. The isolation gate structure can be part of any standard cell being placed at a cell boundary or inside the cell to provide access to backside signal routing. Additionally, filler cells with isolation gate structures may provide backside routing connections for adjacent functional cells.

公开(公告)号：US20230005908A1

公开(公告)日：2023-01-05

申请号：US17930188

申请日：2022-09-07

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Thomas Hoffmann

IPC: H01L27/088 ,  H01L27/02 ,  G06F30/398

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

公开(公告)号：US10700065B2

公开(公告)日：2020-06-30

申请号：US16156461

申请日：2018-10-10

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Thomas Hoffmann

IPC: H01L27/088 ,  H01L27/02 ,  G06F30/398

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

公开(公告)号：US20250107229A1

公开(公告)日：2025-03-27

申请号：US18888284

申请日：2024-09-18

Applicant: Apple Inc.

Inventor： Xin Miao ,  Emre Alptekin

IPC: H01L27/092

Abstract: Device layouts for integrated circuit devices that include threshold voltage shift induced by placement of alternate work function metals adjacent active gates are disclosed. The device layouts include a single epitaxy for active regions in the device with common source/drain regions among the active region rows in the layouts. Metal gate sections above one or more rows of active regions may be replaced with metal of a different work function in inactive regions of the layout. The different work function metal in the inactive regions will induce threshold voltage shift in adjacent (neighboring) active transistors of the device layouts.

公开(公告)号：US20240107737A1

公开(公告)日：2024-03-28

申请号：US18448607

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Saurabh P. Sinha ,  Emre Alptekin ,  Xin Miao

IPC: H10B10/00

CPC classification number: H10B10/125

Abstract: A SRAM cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing along with stacked transistors to provide multiple transistors for implementation of inverters and pass gates in a memory cell. Various connection routes between components of the transistors (e.g., gates, sources, and drains) are made to allow cross-coupling between inverters in the memory cell.

公开(公告)号：US20240107738A1

公开(公告)日：2024-03-28

申请号：US18448634

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Saurabh P. Sinha ,  Shahzad Nazar ,  Xin Miao ,  Emre Alptekin

IPC: H10B10/00

CPC classification number: H10B10/125 ,  H10B10/18

Abstract: A memory device layout that implements SRAM cells with stacked transistors is disclosed. The memory utilizes both topside metal routing and backside metal routing for routing of bitlines between bit cells with stacked transistors and logic cells coupled to the bit cells.

公开(公告)号：US20200118999A1

公开(公告)日：2020-04-16

申请号：US16156461

申请日：2018-10-10

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Thomas Hoffmann

IPC: H01L27/088 ,  H01L27/02 ,  G06F17/50

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

公开(公告)号：US20240105709A1

公开(公告)日：2024-03-28

申请号：US18448573

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Saurabh P. Sinha ,  Xin Miao ,  Emre Alptekin

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L27/0922 ,  H10B10/12

Abstract: A cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing. Various connection routes between components of the transistors (e.g., gates, sources, and drains) and either the topside metal routing or the backside metal routing can be made. The specific connection routes can be determined based on a desired device construction. Thus, the cell layout disclosed enables various devices to be constructed based on a basic cell structure.

公开(公告)号：US20200328205A1

公开(公告)日：2020-10-15

申请号：US16913770

申请日：2020-06-26

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Thomas Hoffmann

IPC: H01L27/088 ,  H01L27/02 ,  G06F30/398

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

公开(公告)号：US11469226B2

公开(公告)日：2022-10-11

申请号：US16913770

申请日：2020-06-26

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Thomas Hoffmann

IPC: H01L27/088 ,  H01L27/02 ,  G06F30/398

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.