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    Stacked SRAM Cell Architecture
    1.
    发明公开
    Stacked SRAM Cell Architecture 审中-公开

    公开(公告)号：US20240107737A1

    公开(公告)日：2024-03-28

    申请号：US18448607

    申请日：2023-08-11

    Applicant: Apple Inc.

    Inventor： Saurabh P. Sinha ,  Emre Alptekin ,  Xin Miao

    IPC: H10B10/00

    CPC classification number: H10B10/125

    Abstract: A SRAM cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing along with stacked transistors to provide multiple transistors for implementation of inverters and pass gates in a memory cell. Various connection routes between components of the transistors (e.g., gates, sources, and drains) are made to allow cross-coupling between inverters in the memory cell.

    Stacked FET Standard Cell Architecture
    3.
    发明公开
    Stacked FET Standard Cell Architecture 审中-公开

    公开(公告)号：US20240105709A1

    公开(公告)日：2024-03-28

    申请号：US18448573

    申请日：2023-08-11

    Applicant: Apple Inc.

    Inventor： Saurabh P. Sinha ,  Xin Miao ,  Emre Alptekin

    IPC: H01L27/02 ,  H01L27/092

    CPC classification number: H01L27/0207 ,  H01L27/0922 ,  H10B10/12

    Abstract: A cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing. Various connection routes between components of the transistors (e.g., gates, sources, and drains) and either the topside metal routing or the backside metal routing can be made. The specific connection routes can be determined based on a desired device construction. Thus, the cell layout disclosed enables various devices to be constructed based on a basic cell structure.

    Buffer and Inverter Transistors Embedded in Interconnect Metal Layers
    4.
    发明申请
    Buffer and Inverter Transistors Embedded in Interconnect Metal Layers 有权

    公开(公告)号：US20250105134A1

    公开(公告)日：2025-03-27

    申请号：US18883389

    申请日：2024-09-12

    Applicant: Apple Inc.

    Inventor： Xin Miao ,  Saurabh P. Sinha

    IPC: H01L23/50 ,  H01L23/535 ,  H01L25/11 ,  H01L29/40 ,  H01L29/423

    Abstract: Integrated circuit devices with buffer transistors or inverter transistors formed between topside BEOL (back end of line) metal layers are described. The buffer or inverter transistors include active regions and source/drains that can be formed in the spaces between topside metal layers. In certain instances, the transistors are formed in between metal layers furthest away from substrate. The transistors connect to routing either above or below the transistors to buffer and/or invert signals passing through the routing. For instance, the transistors may include active regions positioned between power and ground routings and connect to signal routing between the power and ground routings to boost and/or to invert the signal propagating along the signal routing. In various instances, the active regions of the transistors are formed by thin channel materials.

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