公开(公告)号：US20250105134A1

公开(公告)日：2025-03-27

申请号：US18883389

申请日：2024-09-12

Applicant: Apple Inc.

Inventor： Xin Miao ,  Saurabh P. Sinha

IPC: H01L23/50 ,  H01L23/535 ,  H01L25/11 ,  H01L29/40 ,  H01L29/423

Abstract: Integrated circuit devices with buffer transistors or inverter transistors formed between topside BEOL (back end of line) metal layers are described. The buffer or inverter transistors include active regions and source/drains that can be formed in the spaces between topside metal layers. In certain instances, the transistors are formed in between metal layers furthest away from substrate. The transistors connect to routing either above or below the transistors to buffer and/or invert signals passing through the routing. For instance, the transistors may include active regions positioned between power and ground routings and connect to signal routing between the power and ground routings to boost and/or to invert the signal propagating along the signal routing. In various instances, the active regions of the transistors are formed by thin channel materials.

公开(公告)号：US20240107738A1

公开(公告)日：2024-03-28

申请号：US18448634

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Saurabh P. Sinha ,  Shahzad Nazar ,  Xin Miao ,  Emre Alptekin

IPC: H10B10/00

CPC classification number: H10B10/125 ,  H10B10/18

Abstract: A memory device layout that implements SRAM cells with stacked transistors is disclosed. The memory utilizes both topside metal routing and backside metal routing for routing of bitlines between bit cells with stacked transistors and logic cells coupled to the bit cells.

公开(公告)号：US20240105709A1

公开(公告)日：2024-03-28

申请号：US18448573

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Saurabh P. Sinha ,  Xin Miao ,  Emre Alptekin

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L27/0922 ,  H10B10/12

Abstract: A cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing. Various connection routes between components of the transistors (e.g., gates, sources, and drains) and either the topside metal routing or the backside metal routing can be made. The specific connection routes can be determined based on a desired device construction. Thus, the cell layout disclosed enables various devices to be constructed based on a basic cell structure.

公开(公告)号：US20250107229A1

公开(公告)日：2025-03-27

申请号：US18888284

申请日：2024-09-18

Applicant: Apple Inc.

Inventor： Xin Miao ,  Emre Alptekin

IPC: H01L27/092

Abstract: Device layouts for integrated circuit devices that include threshold voltage shift induced by placement of alternate work function metals adjacent active gates are disclosed. The device layouts include a single epitaxy for active regions in the device with common source/drain regions among the active region rows in the layouts. Metal gate sections above one or more rows of active regions may be replaced with metal of a different work function in inactive regions of the layout. The different work function metal in the inactive regions will induce threshold voltage shift in adjacent (neighboring) active transistors of the device layouts.

公开(公告)号：US20240107737A1

公开(公告)日：2024-03-28

申请号：US18448607

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Saurabh P. Sinha ,  Emre Alptekin ,  Xin Miao

IPC: H10B10/00

CPC classification number: H10B10/125

Abstract: A SRAM cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing along with stacked transistors to provide multiple transistors for implementation of inverters and pass gates in a memory cell. Various connection routes between components of the transistors (e.g., gates, sources, and drains) are made to allow cross-coupling between inverters in the memory cell.

公开(公告)号：US20240105727A1

公开(公告)日：2024-03-28

申请号：US18448746

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Xin Miao ,  Praveen Raghavan ,  Thomas Hoffmann ,  Saurabh P. Sinha

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11851 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include cells that form inverter devices, NAND devices, and MUX (multiplexer) devices. The disclosed cells include two or four vertical transistors with various connections made to the transistors that include either connected gate logic for inverter and NAND devices or disconnected gate logic for MUX devices.

公开(公告)号：US20240105617A1

公开(公告)日：2024-03-28

申请号：US18448715

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Xin Miao ,  Praveen Raghavan ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/42376 ,  H01L29/7827

Abstract: Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include a building block cell with a metal contact layer between the backside metal routing and the vertical transistors. Various connections can be made within the building block cell to form more complex structures such as, but not limited to, inverter devices, NAND devices, and MUX (multiplexer) devices.