公开(公告)号：US11243598B2

公开(公告)日：2022-02-08

申请号：US16426633

申请日：2019-05-30

Applicant: Apple Inc.

Inventor： Tatsuya Iwamoto ,  Jason P. Jane ,  Rohan Sanjeev Patil ,  Kutty Banerjee ,  Subodh Asthana ,  Kyle J. Haughey

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06T1/20 ,  G06F17/18 ,  G06F1/3228

Abstract: Systems, methods, and computer readable media to manage power for a graphics processor are described. When the power management component determines the graphics processor is idle when processing a current frame by the graphics processor, the power management component predicts an idle period for the graphics processor based on the work history. The power management component obtains a first latency value indicative of a power on time period and a second latency value indicative of a power off time period for a graphics processor component, such as graphics processor hardware. The power management component provides power instructions to transition the graphics processor component to the power off state based on a determination that a combined latency value of the first latency value and the second latency value is less than the idle period.