公开(公告)号：US11243598B2

公开(公告)日：2022-02-08

申请号：US16426633

申请日：2019-05-30

Applicant: Apple Inc.

Inventor： Tatsuya Iwamoto ,  Jason P. Jane ,  Rohan Sanjeev Patil ,  Kutty Banerjee ,  Subodh Asthana ,  Kyle J. Haughey

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06T1/20 ,  G06F17/18 ,  G06F1/3228

Abstract: Systems, methods, and computer readable media to manage power for a graphics processor are described. When the power management component determines the graphics processor is idle when processing a current frame by the graphics processor, the power management component predicts an idle period for the graphics processor based on the work history. The power management component obtains a first latency value indicative of a power on time period and a second latency value indicative of a power off time period for a graphics processor component, such as graphics processor hardware. The power management component provides power instructions to transition the graphics processor component to the power off state based on a determination that a combined latency value of the first latency value and the second latency value is less than the idle period.

公开(公告)号：US20200104968A1

公开(公告)日：2020-04-02

申请号：US16202689

申请日：2018-11-28

Applicant: Apple Inc.

Inventor： Jason P. Jane ,  Michael J. Swift

IPC: G06T1/20 ,  G06T1/60

Abstract: Systems, methods, and computer readable media to perform out-of-order command scheduling for a graphics processor are described. A graphics driver receives commands committed to a graphics processor for execution. The graphics driver queues a first command to a first graphics driver virtual channel that submits commands to the graphics processor for execution. The first command is associated with a first set of resources. The graphics driver determines whether a second set of resources associated with the second command depends on the first set of resources. The graphics driver queues the second command to the first graphics driver virtual channel based on a determination that the second set of resources depends on the first set of resources. The graphics driver queues the second command to a second virtual channel based on a determination that the second set of resources does not depend on the first set of resources.

公开(公告)号：US20250103122A1

公开(公告)日：2025-03-27

申请号：US18807525

申请日：2024-08-16

Applicant: Apple Inc.

Inventor： Angel E. Socarras ,  Ben D. Jarrett ,  Jason P. Jane ,  Thomas B. Pringle ,  Andrea Gianarro ,  Jackson Dsouza

IPC: G06F1/3206 ,  G06F11/34 ,  G06F11/36

Abstract: Techniques are disclosed relating to power management in a processing circuit that includes a set of functional blocks and performance counter registers configured to store utilization values indicative of utilization of associated ones of the set of functional blocks. A register interface circuit is configured to periodically sample the processing circuit to obtain aggregated utilization values generated from utilization values stored in the performance counter registers and write the aggregated utilization values to the set of trace buffer. A power management processor is configured to utilize a set of information stored in the set of trace buffers to determine whether to change a performance state of the processing circuit, the set of information including time-domain and frequency-domain representations of utilization of the processing circuit. In other embodiments, a functional block that is a hardware limiter of the processing circuit may be determined.

公开(公告)号：US09927863B1

公开(公告)日：2018-03-27

申请号：US15132870

申请日：2016-04-19

Applicant: Apple Inc.

Inventor： Jason P. Jane

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/325 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/16 ,  Y02D10/171

Abstract: In one embodiment, a system includes a power management controller that controls a duty cycle of a processor to manage power. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. Before powering the processor up, the power management control may determine whether or not there is work for the processor to perform. If there is no work to perform, the power management control may delay powering the processor up until there is work to perform, saving additional power. This additional power savings may be tracked, and may serve as a “credit” for the processor when subsequently powered up again.

公开(公告)号：US10229471B2

公开(公告)日：2019-03-12

申请号：US15248499

申请日：2016-08-26

Applicant: Apple, Inc.

Inventor： Gokhan Avkarogullari ,  Jason P. Jane ,  Alex Kan

IPC: G06T1/20 ,  G06F1/3215 ,  G06F1/3234

Abstract: Power management techniques include a graphics processing unit (GPU) in which the GPU determines whether it is operating outside an operational limit and, when the GPU is operating outside the operational limit, the GPU alters performance of an operation to be performed texture processor within the GPU to reduce complexity of the operation. Otherwise, the GPU may perform the texture processing operation at its default complexity. These techniques provide a degree of power control not available in other techniques.

公开(公告)号：US20170061570A1

公开(公告)日：2017-03-02

申请号：US15248499

申请日：2016-08-26

Applicant: Apple, Inc.

Inventor： Gokhan Avkarogullari ,  Jason P. Jane ,  Alex Kan

IPC: G06T1/20 ,  G06T11/00 ,  G06F1/32 ,  G06T7/40

CPC classification number: G06T1/20 ,  G06F1/3215 ,  G06F1/325

Abstract: Power management techniques are disclosed for a graphics processing unit (GPU) in which the GPU determines whether it is operating outside an operational limit and, when the GPU is operating outside the operational limit, the GPU alters performance of an operation to be performed texture processor within the GPU to reduce complexity of the operation. Otherwise, the GPU may perform the texture processing operation at its default complexity. These techniques provide a degree of power control not available in other techniques.

Abstract translation: 电源管理技术被公开用于图形处理单元（GPU），其中GPU确定其是否在操作限制之外操作，并且当GPU在操作限制之外操作时，GPU改变要执行的操作的性能纹理处理器 在GPU内降低操作的复杂性。 否则，GPU可以以其默认的复杂度执行纹理处理操作。 这些技术提供了在其他技术中不可用的一定程度的功率控制。

公开(公告)号：US09348393B1

公开(公告)日：2016-05-24

申请号：US14471245

申请日：2014-08-28

Applicant: Apple Inc.

Inventor： Jason P. Jane

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/325 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/16 ,  Y02D10/171

Abstract: In one embodiment, a system includes a power management controller that controls a duty cycle of a processor to manage power. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. Before powering the processor up, the power management control may determine whether or not there is work for the processor to perform. If there is no work to perform, the power management control may delay powering the processor up until there is work to perform, saving additional power. This additional power savings may be tracked, and may serve as a “credit” for the processor when subsequently powered up again.

Abstract translation: 在一个实施例中，系统包括控制处理器管理电力的占空比的电力管理控制器。 通过在一段时间内频繁地加电和断电处理器，可以控制处理器的功耗，同时提供处理器持续可用的感知。 在为处理器供电之前，电源管理控制可以确定处理器是否有工作来执行。 如果没有工作要执行，则电源管理控制可能会延迟给处理器供电，直到执行工作，从而节省额外的电量。 可以跟踪额外的功率节省，并且可以在随后再次通电时用作处理器的“信用”。

公开(公告)号：US10692169B2

公开(公告)日：2020-06-23

申请号：US16202689

申请日：2018-11-28

Applicant: Apple Inc.

Inventor： Jason P. Jane ,  Michael J. Swift

IPC: G06T1/20 ,  G06T1/60

Abstract: Systems, methods, and computer readable media to perform out-of-order command scheduling for a graphics processor are described. A graphics driver receives commands committed to a graphics processor for execution. The graphics driver queues a first command to a first graphics driver virtual channel that submits commands to the graphics processor for execution. The first command is associated with a first set of resources. The graphics driver determines whether a second set of resources associated with the second command depends on the first set of resources. The graphics driver queues the second command to the first graphics driver virtual channel based on a determination that the second set of resources depends on the first set of resources. The graphics driver queues the second command to a second virtual channel based on a determination that the second set of resources does not depend on the first set of resources.

公开(公告)号：US09952655B1

公开(公告)日：2018-04-24

申请号：US15177793

申请日：2016-06-09

Applicant: Apple Inc.

Inventor： Jason P. Jane ,  Richard W. Schreyer ,  Michael J. E. Swift ,  Gokhan Avkarogullari ,  Luc R. Semeria ,  Patrick Y. Law

IPC: G06F9/30 ,  G06T1/20 ,  G06F1/28 ,  G06F1/32 ,  G06F9/4401 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3246 ,  G06F9/30145 ,  G06F9/442 ,  G06T1/20 ,  G06T2200/28

Abstract: In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator that may control whether or not the GPU captures and/or responds to communications from another processor (e.g. a central processing unit (CPU) that executes a driver associate with the GPU). A snooze indicator may control whether or not the GPU is automatically repowered at the start of the next frame, or is repowered only if the communication indicating additional work has been received. In an embodiment, the GPU mode controls discussed above may permit the GPU firmware executed with the GPU itself to control duty cycle power down, independent of the driver executing on the CPU.