公开(公告)号：US20240231758A1

公开(公告)日：2024-07-11

申请号：US18417868

申请日：2024-01-19

Applicant: Apple Inc.

Inventor： Shahzad Nazar ,  Bharan Giridhar ,  Mohamed H. Abu-Rahma ,  Ajay Bhatia ,  Mayur V. Joshi ,  Yildiz Sinangil ,  Aravind Kandala

IPC: G06F7/544 ,  G06F7/523 ,  G06F17/15 ,  G06N20/00 ,  H03M1/46

CPC classification number: G06F7/5443 ,  G06F7/523 ,  G06F17/15 ,  H03M1/46 ,  G06N20/00

Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.

公开(公告)号：US11914973B2

公开(公告)日：2024-02-27

申请号：US16953093

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Shahzad Nazar ,  Bharan Giridhar ,  Mohamed H. Abu-Rahma ,  Ajay Bhatia ,  Mayur V. Joshi ,  Yildiz Sinangil ,  Aravind Kandala

IPC: G06F7/544 ,  G06F7/523 ,  H03M1/46 ,  G06F17/15 ,  G06N20/00

CPC classification number: G06F7/5443 ,  G06F7/523 ,  G06F17/15 ,  H03M1/46 ,  G06N20/00

Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of the global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit.

公开(公告)号：US20220156045A1

公开(公告)日：2022-05-19

申请号：US16953093

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Shahzad Nazar ,  Bharan Giridhar ,  Mohamed H. Abu-Rahma ,  Ajay Bhatia ,  Mayur V. Joshi ,  Yildiz Sinangil ,  Aravind Kandala

IPC: G06F7/544 ,  G06F7/523 ,  G06F17/15 ,  H03M1/46

Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.