公开(公告)号：US20240223136A1

公开(公告)日：2024-07-04

申请号：US18148293

申请日：2022-12-29

Applicant: Apple Inc.

Inventor： Mina Mofreh Gad Elsayed Abdallah

IPC: H03F3/19 ,  H03G3/30 ,  H04B1/40

CPC classification number: H03F3/19 ,  H03G3/3036 ,  H04B1/40 ,  H03F2200/451 ,  H03G2201/103 ,  H03G2201/307

Abstract: An electronic device with wireless circuitry is provided. The wireless circuitry can include a radio-frequency data converter block configured to receive baseband signals and to output corresponding radio-frequency signals to a radio-frequency power amplifier. The radio-frequency data converter block may include one or more radio-frequency digital-to-analog converter (DAC) cells configured to receive an oscillator signal. The radio-frequency data converter block can exhibit a gain that is controlled using gain control circuitry. The gain control circuitry can control the gain of the radio-frequency data converter block by selectively enabling switchable components within each DAC cell to realize an incremental gain step of a first resolution and by adjusting the duty cycle of the oscillator signal to realize an incremental gain step of a second resolution finer than the first resolution.

公开(公告)号：US20250096743A1

公开(公告)日：2025-03-20

申请号：US18470561

申请日：2023-09-20

Applicant: Apple Inc.

Inventor： Ahmed G Radwan ,  Mina Mofreh Gad Elsayed Abdallah

IPC: H03F1/56 ,  H03F3/19

Abstract: Wireless circuitry can include a radio-frequency amplifier and a tunable matching network coupled to an output of the radio-frequency amplifier. The tunable matching network can include series inductors, first switches coupled between the output of the radio-frequency amplifier and a first portion of the series inductors, and second switches coupled between the first portion of the series inductors and an output port of the tunable matching network. The tunable matching network can further include an adjustable balun having a primary coil coupled to a second portion of the series inductors and having a secondary coil. The wireless circuitry can include control circuitry configured to activate and deactivate the first and second switches to operate the tunable matching network across a wide range of frequency bands.

公开(公告)号：US20250021121A1

公开(公告)日：2025-01-16

申请号：US18349792

申请日：2023-07-10

Applicant: Apple Inc.

Inventor： Adrien Vargas ,  Jerome Casters ,  Guillaume Gourlat ,  Timo W. Gossmann ,  Mina Mofreh Gad Elsayed Abdallah

IPC: G05F1/575 ,  H03K17/687 ,  H03K19/173 ,  H04B1/40

Abstract: Voltage regulator circuitry is provided that includes a pass transistor, an error amplifier for regulating the pass transistor, a high rail switch coupled between a first power supply line and the pass transistor, a big low rail switch coupled between a second power supply line and the pass transistor, a small low rail switch coupled between the second power supply line and the pass transistor, and a comparator for monitor a current flowing through or a voltage across the small low rail switch. The small low rail switch, the comparator, and a gating logic can be coupled in an analog feedback loop. The voltage regulator circuitry can include a sequencer for controlling the high rail switch, the big low rail switch, and the gating logic to perform fast seamless transitions between a low voltage rail mode and a high voltage rail mode without incurring large current glitches.

公开(公告)号：US20240103550A1

公开(公告)日：2024-03-28

申请号：US18102643

申请日：2023-01-27

Applicant: Apple Inc.

Inventor： Guillaume Gourlat ,  Mina Mofreh Gad Elsayed Abdallah ,  Adrien F Vargas

IPC: G05F1/565 ,  G05F3/26

CPC classification number: G05F1/565 ,  G05F3/26

Abstract: A fast loop amplifier provides low-dropout (LDO) regulation for a frequency range. In one embodiment, the fast loop amplifier may include a two-stage amplifier that decouples gain from bandwidth. In another embodiment, the LDO regulator may include an alternating current coupling capacitor having increased capacitance (e.g., twice that of a load capacitance) and adding one or more gate blocking capacitors. The load capacitance may include a sum of a capacitance of the one or more gate blocking capacitors and parasitic capacitances of the fast loop amplifier. The AC coupling capacitor and the one or more gate blocking capacitors may improve base open-loop power supply rejection ratio and load regulation. In yet another embodiment, bias generation circuitry of the fast loop amplifier may include an amplifier coupled to the fast loop amplifier that reduces gain variations across process, voltage, and/or temperature, and maintains current density with respect to gain programing.