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公开(公告)号：US10345846B1
公开(公告)日：2019-07-09
申请号：US15902308
申请日：2018-02-22
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Daniel J. Fritchman
Abstract: A reference voltage generation circuit (or bandgap circuit) having a flipped-gate transistor is disclosed. A bandgap circuit according to the disclosure includes first, second, third and fourth transistors. The first transistor is a flipped-gate transistor having a gate terminal of an opposite polarity (e.g., an n-channel metal oxide semiconductor, or NMOS, transistor having a gate terminal with a p-type polysilicon implant). The second third and fourth transistors have a corresponding type polysilicon implants (e.g., NMOS transistors having respective gate terminals with an n-type polysilicon implant). The circuit is configured to generate a reference voltage equal to a sum of gate-source voltages of the first and third transistors, minus respective gate-source voltages of the second and fourth transistors.
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公开(公告)号：US20230092906A1
公开(公告)日：2023-03-23
申请号：US17482302
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz
Abstract: A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.
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公开(公告)号：US12278886B2
公开(公告)日：2025-04-15
申请号：US18313729
申请日：2023-05-08
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz
Abstract: A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.
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公开(公告)号：US20230283449A1
公开(公告)日：2023-09-07
申请号：US18313729
申请日：2023-05-08
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz
CPC classification number: H04L7/0079 , H04L7/0016 , H04L25/03878
Abstract: A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.
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公开(公告)号：US12244683B2
公开(公告)日：2025-03-04
申请号：US18319421
申请日：2023-05-17
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj
Abstract: A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The sample circuit may sample a serial data stream at different times that correspond to even-numbered and odd-numbered symbols in the serial data stream. The recovery circuit may use different coefficients to process the respective samples of the even-numbered and odd-numbered symbols in order to recover the data symbols encoded in the serial data stream.
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Patent Agency Ranking
公开(公告)号：US12052335B2
公开(公告)日：2024-07-30
申请号：US18161995
申请日：2023-01-31
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj
CPC classification number: H04L7/0058 , H04L7/0062 , H04L7/02 , H04L7/0066
Abstract: A serial data receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. During startup of a communication channel, phase information generated by the analog receiver circuit may be used to generate clock signals for the ADC-based receiver circuit. After a period of time, the ADC-based receiver circuit can generate its own phase information to be used in the generation of the clock signals.
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公开(公告)号：US11689351B2
公开(公告)日：2023-06-27
申请号：US17482302
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz
CPC classification number: H04L7/0079 , H04L7/0016 , H04L25/03878
Abstract: A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.
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公开(公告)号：US20230093114A1
公开(公告)日：2023-03-23
申请号：US17482322
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz , Shah M. Sharif
IPC: H03M1/06
Abstract: A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.
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公开(公告)号：US20240097875A1
公开(公告)日：2024-03-21
申请号：US18161995
申请日：2023-01-31
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj
CPC classification number: H04L7/0058 , H04L7/0062 , H04L7/02 , H04L7/0066
Abstract: A serial data receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. During startup of a communication channel, phase information generated by the analog receiver circuit may be used to generate clock signals for the ADC-based receiver circuit. After a period of time, the ADC-based receiver circuit can generate its own phase information to be used in the generation of the clock signals.
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公开(公告)号：US20240097874A1
公开(公告)日：2024-03-21
申请号：US18319421
申请日：2023-05-17
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj
CPC classification number: H04L7/0029 , H04B1/04 , H04L7/033
Abstract: A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The sample circuit may sample a serial data stream at different times that correspond to even-numbered and odd-numbered symbols in the serial data stream. The recovery circuit may use different coefficients to process the respective samples of the even-numbered and odd-numbered symbols in order to recover the data symbols encoded in the serial data stream.
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