GLITCH LESS DELAY CIRCUIT FOR REAL-TIME DELAY ADJUSTMENTS
    1.
    发明申请
    GLITCH LESS DELAY CIRCUIT FOR REAL-TIME DELAY ADJUSTMENTS 有权
    GLITCH LESS DELAY CIRCUIT用于实时延迟调整

    公开(公告)号:US20160094230A1

    公开(公告)日:2016-03-31

    申请号:US14497376

    申请日:2014-09-26

    Applicant: Apple Inc.

    CPC classification number: H03L7/0818 H03K5/01 H03L7/0814

    Abstract: An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal.

    Abstract translation: 公开了一种装置,其中时钟信号可以通过延迟电路传播。 延迟电路可以包括第一和第二延迟级,其中根据对每个延迟级的相应控制信号的值,每个延迟级可以被编程为两个延迟时间中的一个。 延迟电路还可以包括可以将相应控制信号的值从第一值改变到第二值的电路。 响应于第一级的输出和第二级的输出相等的确定,电路可以改变相应控制信号的值。

    Glitch less delay circuit for real-time delay adjustments
    2.
    发明授权
    Glitch less delay circuit for real-time delay adjustments 有权
    毛刺更短的延迟电路用于实时延迟调整

    公开(公告)号:US09490821B2

    公开(公告)日:2016-11-08

    申请号:US14497376

    申请日:2014-09-26

    Applicant: Apple Inc.

    CPC classification number: H03L7/0818 H03K5/01 H03L7/0814

    Abstract: An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal.

    Abstract translation: 公开了一种装置,其中时钟信号可以通过延迟电路传播。 延迟电路可以包括第一和第二延迟级,其中根据对每个延迟级的相应控制信号的值,每个延迟级可以被编程为两个延迟时间中的一个。 延迟电路还可以包括可以将相应控制信号的值从第一值改变为第二值的电路。 响应于第一级的输出和第二级的输出相等的确定,电路可以改变相应控制信号的值。

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