公开(公告)号：US09395747B1

公开(公告)日：2016-07-19

申请号：US14592146

申请日：2015-01-08

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Gregoire J. Le Grand de Mercey

IPC: H03L7/00 ,  G06F1/12

CPC classification number: G06F1/12

Abstract: Various embodiments of a clock generator are disclosed. An example system may include a functional unit, and a clock generation unit configured to adjust a frequency of an output clock signal responsive to an assertion of an enable signal from the functional unit. The clock generation unit may also be configured to halt the output clock signal responsive to a de-assertion of the enable signal by the functional unit and to restart the output clock signal responsive to a determination that a first predetermined amount of time has elapsed since the output clock signal was halted. The clock generation unit may be further configured to adjust the frequency of the output clock signal responsive to restarting the output clock signal, and to halt the output clock signal responsive to a determination that the frequency of the output clock signal is within a predetermined frequency range that includes the target frequency.

Abstract translation: 公开了时钟发生器的各种实施例。 示例性系统可以包括功能单元，以及时钟生成单元，被配置为响应于来自功能单元的使能信号的断言来调整输出时钟信号的频率。 时钟生成单元还可以被配置为响应于功能单元的使能信号的断言而停止输出时钟信号，并且响应于从第一预定时间量过去的确定重新启动输出时钟信号 输出时钟信号停止。 时钟生成单元还可以被配置为响应于重新启动输出时钟信号来调整输出时钟信号的频率，并响应于输出时钟信号的频率在预定频率范围内的确定而停止输出时钟信号 包括目标频率。

公开(公告)号：US09490821B2

公开(公告)日：2016-11-08

申请号：US14497376

申请日：2014-09-26

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Gregoire J. Le Grand de Mercey ,  Yair R. Koren ,  Jung Wan Kim

IPC: H03L7/06 ,  H03L7/081 ,  H03K5/01

CPC classification number: H03L7/0818 ,  H03K5/01 ,  H03L7/0814

Abstract: An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal.

Abstract translation: 公开了一种装置，其中时钟信号可以通过延迟电路传播。 延迟电路可以包括第一和第二延迟级，其中根据对每个延迟级的相应控制信号的值，每个延迟级可以被编程为两个延迟时间中的一个。 延迟电路还可以包括可以将相应控制信号的值从第一值改变为第二值的电路。 响应于第一级的输出和第二级的输出相等的确定，电路可以改变相应控制信号的值。

公开(公告)号：US20160202723A1

公开(公告)日：2016-07-14

申请号：US14592146

申请日：2015-01-08

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Gregoire J. Le Grand de Mercey

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: Various embodiments of a clock generator are disclosed. An example system may include a functional unit, and a clock generation unit configured to adjust a frequency of an output clock signal responsive to an assertion of an enable signal from the functional unit. The clock generation unit may also be configured to halt the output clock signal responsive to a de-assertion of the enable signal by the functional unit and to restart the output clock signal responsive to a determination that a first predetermined amount of time has elapsed since the output clock signal was halted. The clock generation unit may be further configured to adjust the frequency of the output clock signal responsive to restarting the output clock signal, and to halt the output clock signal responsive to a determination that the frequency of the output clock signal is within a predetermined frequency range that includes the target frequency.

Abstract translation: 公开了时钟发生器的各种实施例。 示例性系统可以包括功能单元，以及时钟生成单元，被配置为响应于来自功能单元的使能信号的断言来调整输出时钟信号的频率。 时钟生成单元还可以被配置为响应于功能单元的使能信号的断言而停止输出时钟信号，并且响应于从第一预定时间量过去的确定重新启动输出时钟信号 输出时钟信号停止。 时钟生成单元还可以被配置为响应于重新启动输出时钟信号而调整输出时钟信号的频率，并响应于输出时钟信号的频率在预定频率范围内的确定而停止输出时钟信号 包括目标频率。

公开(公告)号：US20160094230A1

公开(公告)日：2016-03-31

申请号：US14497376

申请日：2014-09-26

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Gregoire J. Le Grand de Mercey ,  Yair R. Koren ,  Jung Wan Kim

IPC: H03L7/081 ,  H03K5/01

CPC classification number: H03L7/0818 ,  H03K5/01 ,  H03L7/0814

Abstract: An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal.

Abstract translation: 公开了一种装置，其中时钟信号可以通过延迟电路传播。 延迟电路可以包括第一和第二延迟级，其中根据对每个延迟级的相应控制信号的值，每个延迟级可以被编程为两个延迟时间中的一个。 延迟电路还可以包括可以将相应控制信号的值从第一值改变到第二值的电路。 响应于第一级的输出和第二级的输出相等的确定，电路可以改变相应控制信号的值。