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公开(公告)号:US20250046689A1
公开(公告)日:2025-02-06
申请号:US18365891
申请日:2023-08-04
Applicant: Apple Inc.
Inventor: Yikang Deng , Yifan Kao , Jun Chung Hsu , Taegui Kim
IPC: H01L23/498 , H01L23/00
Abstract: Routing substrates, methods of manufacture, and electronic assemblies including routing substrates are described. In an embodiment, a routing substrate includes a plurality of metal routing layers, a plurality of dielectric layers including a top dielectric layer forming a topmost surface, and a cavity formed in the topmost surface. The cavity may include a bottom cavity surface, a first plurality of first surface mount (SMT) metal bumps embedded within the top dielectric layer and protruding from the topmost surface of the top dielectric layer, and a second plurality of second SMT metal bumps embedded within an intermediate dielectric layer of the plurality of dielectric layers and protruding from the bottom cavity surface.
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公开(公告)号:US20240162182A1
公开(公告)日:2024-05-16
申请号:US18513167
申请日:2023-11-17
Applicant: Apple Inc.
Inventor: Yikang Deng , Taegui Kim , Yifan Kao , Jun Chung Hsu
IPC: H01L23/00 , H01L23/498 , H01L25/00 , H01L25/065
CPC classification number: H01L24/24 , H01L23/49827 , H01L24/25 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L23/13 , H01L2224/24011 , H01L2224/24227 , H01L2224/2518 , H01L2224/82005 , H01L2225/06524 , H01L2225/06548 , H01L2225/06572 , H01L2924/15153 , H01L2924/19011
Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.
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公开(公告)号:US11862597B2
公开(公告)日:2024-01-02
申请号:US17482967
申请日:2021-09-23
Applicant: Apple Inc.
Inventor: Yikang Deng , Taegui Kim , Yifan Kao , Jun Chung Hsu
IPC: H01L23/498 , H01L25/065 , H01L23/00 , H01L25/00 , H01L23/13
CPC classification number: H01L24/24 , H01L23/49827 , H01L24/25 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L23/13 , H01L2224/2401 , H01L2224/24227 , H01L2224/2518 , H01L2224/82005 , H01L2225/06524 , H01L2225/06548 , H01L2225/06572 , H01L2924/15153 , H01L2924/19011
Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.
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公开(公告)号:US20230092505A1
公开(公告)日:2023-03-23
申请号:US17482967
申请日:2021-09-23
Applicant: Apple Inc.
Inventor: Yikang Deng , Taegui Kim , Yifan Kao , Jun Chung Hsu
IPC: H01L23/00 , H01L23/498 , H01L25/065 , H01L25/00
Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.
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