公开(公告)号：US11545455B2

公开(公告)日：2023-01-03

申请号：US16423931

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US11862597B2

公开(公告)日：2024-01-02

申请号：US17482967

申请日：2021-09-23

Applicant: Apple Inc.

Inventor： Yikang Deng ,  Taegui Kim ,  Yifan Kao ,  Jun Chung Hsu

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/13

CPC classification number: H01L24/24 ,  H01L23/49827 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/13 ,  H01L2224/2401 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2224/82005 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15153 ,  H01L2924/19011

Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.

公开(公告)号：US20250046689A1

公开(公告)日：2025-02-06

申请号：US18365891

申请日：2023-08-04

Applicant: Apple Inc.

Inventor： Yikang Deng ,  Yifan Kao ,  Jun Chung Hsu ,  Taegui Kim

IPC: H01L23/498 ,  H01L23/00

Abstract: Routing substrates, methods of manufacture, and electronic assemblies including routing substrates are described. In an embodiment, a routing substrate includes a plurality of metal routing layers, a plurality of dielectric layers including a top dielectric layer forming a topmost surface, and a cavity formed in the topmost surface. The cavity may include a bottom cavity surface, a first plurality of first surface mount (SMT) metal bumps embedded within the top dielectric layer and protruding from the topmost surface of the top dielectric layer, and a second plurality of second SMT metal bumps embedded within an intermediate dielectric layer of the plurality of dielectric layers and protruding from the bottom cavity surface.

公开(公告)号：US20240162182A1

公开(公告)日：2024-05-16

申请号：US18513167

申请日：2023-11-17

Applicant: Apple Inc.

Inventor： Yikang Deng ,  Taegui Kim ,  Yifan Kao ,  Jun Chung Hsu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L23/49827 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/13 ,  H01L2224/24011 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2224/82005 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15153 ,  H01L2924/19011

Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.

公开(公告)号：US20240356225A1

公开(公告)日：2024-10-24

申请号：US18306063

申请日：2023-04-24

Applicant: Apple Inc.

Inventor： Trang T. Thai ,  Jennifer M. Edwards ,  Sidharth S. Dalmia ,  Menglu Li ,  Taegui Kim ,  Hai H. Ta

IPC: H01Q9/04 ,  H01Q1/14 ,  H01Q1/48 ,  H01Q1/50 ,  H01Q23/00

CPC classification number: H01Q9/0407 ,  H01Q1/14 ,  H01Q1/48 ,  H01Q1/50 ,  H01Q23/00

Abstract: An electronic device may be provided with a phased antenna array with antennas on an antenna module. The module may include a primary substrate and a secondary substrate mounted to the primary substrate by an interconnect. An antenna may include patch elements in the primary substrate and patch elements in the secondary substrate that are fed using conductive vias. Fences of conductive vias may couple the patch elements in the primary substrate to ground to isolate the patch elements in the primary substrate from the patch elements in the secondary substrate. The secondary substrate may be smaller than the primary substrate, allowing the secondary substrate to fit into relatively small portions of the electronic device while locating the patch elements in the secondary substrates closer to free space, thereby maximizing antenna performance.

公开(公告)号：US20230115986A1

公开(公告)日：2023-04-13

申请号：US18046134

申请日：2022-10-12

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US11908819B2

公开(公告)日：2024-02-20

申请号：US18046134

申请日：2022-10-12

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/498 ,  H01L24/11 ,  H01L24/13 ,  H01L24/25 ,  H01L24/26 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/11003 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14517 ,  H01L2224/16112 ,  H01L2224/24996 ,  H01L2224/2501 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/73204 ,  H01L2224/83051

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US20230092505A1

公开(公告)日：2023-03-23

申请号：US17482967

申请日：2021-09-23

Applicant: Apple Inc.

Inventor： Yikang Deng ,  Taegui Kim ,  Yifan Kao ,  Jun Chung Hsu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00

Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.

公开(公告)号：US20200381383A1

公开(公告)日：2020-12-03

申请号：US16423931

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.