公开(公告)号：US20250046689A1

公开(公告)日：2025-02-06

申请号：US18365891

申请日：2023-08-04

Applicant: Apple Inc.

Inventor： Yikang Deng ,  Yifan Kao ,  Jun Chung Hsu ,  Taegui Kim

IPC: H01L23/498 ,  H01L23/00

Abstract: Routing substrates, methods of manufacture, and electronic assemblies including routing substrates are described. In an embodiment, a routing substrate includes a plurality of metal routing layers, a plurality of dielectric layers including a top dielectric layer forming a topmost surface, and a cavity formed in the topmost surface. The cavity may include a bottom cavity surface, a first plurality of first surface mount (SMT) metal bumps embedded within the top dielectric layer and protruding from the topmost surface of the top dielectric layer, and a second plurality of second SMT metal bumps embedded within an intermediate dielectric layer of the plurality of dielectric layers and protruding from the bottom cavity surface.

公开(公告)号：US20240162182A1

公开(公告)日：2024-05-16

申请号：US18513167

申请日：2023-11-17

Applicant: Apple Inc.

Inventor： Yikang Deng ,  Taegui Kim ,  Yifan Kao ,  Jun Chung Hsu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L23/49827 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/13 ,  H01L2224/24011 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2224/82005 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15153 ,  H01L2924/19011

Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.

公开(公告)号：US10991659B2

公开(公告)日：2021-04-27

申请号：US16704671

申请日：2019-12-05

Applicant: Apple Inc.

Inventor： Flynn P. Carson ,  Jun Chung Hsu ,  Meng Chi Lee ,  Shatki S. Chauhan

IPC: H01L23/552 ,  H01L21/78 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L23/00

Abstract: Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

公开(公告)号：US20170025361A1

公开(公告)日：2017-01-26

申请号：US14947353

申请日：2015-11-20

Applicant: Apple Inc.

Inventor： Meng Chi Lee ,  Shakti S. Chauhan ,  Flynn P. Carson ,  Jun Chung Hsu ,  Tha-An Lin

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/81

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed over the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The substrate of the SiP may include at least some metallization along vertical walls in the end portions of the substrate. The metallization may provide a large contact area for coupling the metal shield to a ground ring coupled to the ground layer in the PCB. The metallization along the vertical walls in the end portions of the substrate may be formed as through-metal vias in a common substrate before singulation to form the SiP.

Abstract translation: 公开了一种封装系统（SiP），其使用EMI屏蔽来抑制SiP内的元件上的EMI或其他电干扰。 可以在SiP上形成金属屏蔽。 金属屏蔽可以电耦合到印刷电路板（PCB）中的接地层，以在SiP周围形成EMI屏蔽。 SiP的衬底可以包括在衬底的端部中沿垂直壁的至少一些金属化。 金属化可以提供用于将金属屏蔽件耦合到耦合到PCB中的接地层的接地环的大的接触面积。 沿着衬底的端部的垂直壁的金属化可以在共形衬底之前形成为通孔金属孔，以形成SiP。

公开(公告)号：US09305853B2

公开(公告)日：2016-04-05

申请号：US14088736

申请日：2013-11-25

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jun Zhai

IPC: H01L23/52 ,  H01L29/40 ,  H01L23/28 ,  H01L23/12 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48 ,  H01L25/10

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/12 ,  H01L23/481 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19106 ,  H01L2924/00

Abstract: A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package.

Abstract translation: 用于PoP（封装封装）的底部封装可以形成有支撑薄的或无芯的衬底的加强层。 加强层可以为基底提供刚度和刚度，以增加底部包装的刚度和刚性，并提供更好的基底处理。 加强层可以使用芯材，层压层和金属层形成。 衬底可以形成在加强层上。 加强层可以包括尺寸适于容纳模具的开口。 裸片可以在开口中耦合到衬底的暴露表面。 通过加强层的金属填充的通孔可以用于将衬底耦合到顶部封装。

公开(公告)号：US11862597B2

公开(公告)日：2024-01-02

申请号：US17482967

申请日：2021-09-23

Applicant: Apple Inc.

Inventor： Yikang Deng ,  Taegui Kim ,  Yifan Kao ,  Jun Chung Hsu

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/13

CPC classification number: H01L24/24 ,  H01L23/49827 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/13 ,  H01L2224/2401 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2224/82005 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15153 ,  H01L2924/19011

Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.

公开(公告)号：US10535611B2

公开(公告)日：2020-01-14

申请号：US15042817

申请日：2016-02-12

Applicant: Apple Inc.

Inventor： Flynn P. Carson ,  Jun Chung Hsu ,  Meng Chi Lee ,  Shakti S. Chauhan

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

Abstract: Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

公开(公告)号：US20170179039A1

公开(公告)日：2017-06-22

申请号：US14976199

申请日：2015-12-21

Applicant: Apple Inc.

Inventor： Meng Chi Lee ,  Shakti S. Chauhan ,  Flynn P. Carson ,  Jun Chung Hsu ,  Tha-An Lin

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/522 ,  H01L21/48 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.

公开(公告)号：US20160172261A1

公开(公告)日：2016-06-16

申请号：US15050110

申请日：2016-02-22

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jun Zhai

IPC: H01L23/13 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/12 ,  H01L23/481 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19106 ,  H01L2924/00

Abstract: A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package.

公开(公告)号：US20160071807A1

公开(公告)日：2016-03-10

申请号：US14518887

申请日：2014-10-20

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jie-Hua Zhao

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A methodology for addressing package warpage is described. In an embodiment a package includes a die mounted on a wiring board. Portion of a metal plane within the wiring board includes a reduced portion, characterized by a reduced thickness that is less than a baseline thickness.

Abstract translation: 描述了解决包装翘曲的方法。 在一个实施例中，封装包括安装在布线板上的管芯。 线路板内的金属平面的一部分包括减少的部分，其特征在于小于基线厚度的厚度减小。