公开(公告)号：US12178146B2

公开(公告)日：2024-12-24

申请号：US18190971

申请日：2023-03-28

Applicant: Applied Materials, Inc.

Inventor： Deepak Kamalanathan ,  Archana Kumar ,  Siddarth Krishnan

IPC: H10N70/20 ,  H10N70/00

Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

公开(公告)号：US11362275B2

公开(公告)日：2022-06-14

申请号：US16855122

申请日：2020-04-22

Applicant: Applied Materials, Inc.

Inventor： Nicolas Louis Gabriel Breil ,  Siddarth Krishnan ,  Shashank Sharma ,  Ria Someshwar ,  Kai Ng ,  Deepak Kamalanathan

IPC: H01L45/00 ,  H01L27/24

Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.

公开(公告)号：US11616195B2

公开(公告)日：2023-03-28

申请号：US16883009

申请日：2020-05-26

Applicant: Applied Materials, Inc.

Inventor： Deepak Kamalanathan ,  Archana Kumar ,  Siddarth Krishnan

IPC: H01L45/00

Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

公开(公告)号：US20210280247A1

公开(公告)日：2021-09-09

申请号：US17329008

申请日：2021-05-24

Applicant: Applied Materials, Inc.

Inventor： Deepak Kamalanathan ,  Siddarth Krishnan ,  Archana Kumar ,  Fuxi Cai ,  Federico Nardi

IPC: G11C13/00

Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

公开(公告)号：US11017856B1

公开(公告)日：2021-05-25

申请号：US16793794

申请日：2020-02-18

Applicant: Applied Materials, Inc.

Inventor： Deepak Kamalanathan ,  Siddarth Krishnan ,  Archana Kumar ,  Fuxi Cai ,  Federico Nardi

IPC: G11C11/00 ,  G11C13/00

Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

公开(公告)号：US20230232727A1

公开(公告)日：2023-07-20

申请号：US18190971

申请日：2023-03-28

Applicant: Applied Materials, Inc.

Inventor： Deepak Kamalanathan ,  Archana Kumar ,  Siddarth Krishnan

IPC: H10N70/20 ,  H10N70/00

CPC classification number: H10N70/245 ,  H10N70/021 ,  H10N70/8833

Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

公开(公告)号：US11127458B1

公开(公告)日：2021-09-21

申请号：US16861204

申请日：2020-04-28

Applicant: Applied Materials, Inc.

Inventor： Deepak Kamalanathan ,  Siddarth Krishnan ,  Fuxi Cai ,  Christophe J Chevallier

IPC: G11C11/56 ,  G11C13/00

Abstract: A method of setting multi-state memory elements into at least one low-power state may include receiving a command to cause a memory element to transition into one of three or more states; applying a first signal to the memory element to transition the memory element into the one of the three or more states, where the three or more states are evenly spaced in a portion of an operating range of the memory element; receiving a command to cause a memory element to transition into a low-power state; applying a second signal to the memory element to transition the memory element into the low-power state, where the low-power state is outside of the portion of the operating range of the memory element by an amount greater than a space between each of the three or more states.

公开(公告)号：US11790989B2

公开(公告)日：2023-10-17

申请号：US17329008

申请日：2021-05-24

Applicant: Applied Materials, Inc.

Inventor： Deepak Kamalanathan ,  Siddarth Krishnan ,  Archana Kumar ,  Fuxi Cai ,  Federico Nardi

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/004 ,  G11C13/0038 ,  G11C13/0069

Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.