公开(公告)号：US11908914B2

公开(公告)日：2024-02-20

申请号：US17376504

申请日：2021-07-15

Applicant: Applied Materials, Inc.

Inventor： Ria Someshwar ,  Seshadri Ganguli ,  Lan Yu ,  Siddarth Krishnan ,  Srinivas Gandikota ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H01L29/45 ,  H01L21/324 ,  H01L21/285 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/456 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/401 ,  H01L29/45 ,  H01L29/665

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

公开(公告)号：US20230115980A1

公开(公告)日：2023-04-13

申请号：US17498373

申请日：2021-10-11

Applicant: Applied Materials, Inc.

Inventor： Michel Khoury ,  Ria Someshwar

IPC: H01L33/00 ,  H01L33/32

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may include a nitrogen-containing nucleation layer deposited on the substrate. The methods may include forming a silicon-containing material on at least a first portion of the nitrogen-containing nucleation layer. The methods may include forming a second layer of material on at least a second portion of the nitrogen-containing nucleation layer. The methods may include forming a masking layer on a portion of the second layer of material. The masking layer may cover less than or about 90% of the second layer of material. The methods may include growing the second layer of material through the masking layer. The methods may include coalescing the second layer of material above the masking layer.

公开(公告)号：US20230124414A1

公开(公告)日：2023-04-20

申请号：US17696447

申请日：2022-03-16

Applicant: Applied Materials, Inc.

Inventor： Michel Khoury ,  Ria Someshwar

IPC: H01L33/00 ,  H01L33/32 ,  H01L33/18

Abstract: Exemplary semiconductor structures may include a silicon-containing substrate. The structures may include a layer of a metal nitride overlying the silicon-containing substrate. The layer of the metal nitride may include a plurality of features. The structures may include a gallium nitride structure overlying the layer of the metal nitride.

公开(公告)号：US20230015781A1

公开(公告)日：2023-01-19

申请号：US17376504

申请日：2021-07-15

Applicant: Applied Materials, Inc.

Inventor： Ria Someshwar ,  Seshadri Ganguli ,  Lan Yu ,  Siddarth Krishnan ,  Srinivas Gandikota ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H01L29/45 ,  H01L29/40 ,  H01L21/285 ,  H01L21/324

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

公开(公告)号：US11362275B2

公开(公告)日：2022-06-14

申请号：US16855122

申请日：2020-04-22

Applicant: Applied Materials, Inc.

Inventor： Nicolas Louis Gabriel Breil ,  Siddarth Krishnan ,  Shashank Sharma ,  Ria Someshwar ,  Kai Ng ,  Deepak Kamalanathan

IPC: H01L45/00 ,  H01L27/24

Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.

公开(公告)号：US20240154018A1

公开(公告)日：2024-05-09

申请号：US18411693

申请日：2024-01-12

Applicant: Applied Materials, Inc.

Inventor： Ria Someshwar ,  Seshadri Ganguli ,  Lan Yu ,  Siddarth Krishnan ,  Srinivas Gandikota ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/456 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/401 ,  H01L29/45 ,  H01L29/665

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

公开(公告)号：US20230299236A1

公开(公告)日：2023-09-21

申请号：US17695206

申请日：2022-03-15

Applicant: Applied Materials, Inc.

Inventor： Michel Khoury ,  Ria Someshwar

IPC: H01L33/32 ,  H01L33/00

CPC classification number: H01L33/32 ,  H01L33/007 ,  H01L33/0095

Abstract: Exemplary semiconductor structures may include a silicon-containing substrate. The structures may include a first layer of a first metal nitride overlying the silicon-containing substrate. The structures may include a second layer of a second metal nitride overlying the first layer of the first metal nitride. The structures may include a gallium nitride structure overlying the layer of the metal nitride.

公开(公告)号：US20230117013A1

公开(公告)日：2023-04-20

申请号：US17507134

申请日：2021-10-21

Applicant: Applied Materials, Inc.

Inventor： Michel Khoury ,  Ria Someshwar

IPC: H01L33/00 ,  H01L33/32

Abstract: Exemplary semiconductor structures may include a silicon-containing substrate. The structures may include a layer of a metal nitride overlying the silicon-containing substrate. The structures may include a gallium nitride structure overlying the layer of the metal nitride. The structures may include an oxygen-containing layer disposed between the layer of the metal nitride and the gallium nitride structure.

公开(公告)号：US20220319836A1

公开(公告)日：2022-10-06

申请号：US17697058

申请日：2022-03-17

Applicant: Applied Materials, Inc.

Inventor： Michael Chudzik ,  Ria Someshwar ,  Daniel Deyo ,  Michel Khoury ,  Sha Zhao

IPC: H01L21/02 ,  H01L21/033

Abstract: Exemplary processing methods include forming a nucleation layer on a substrate. The nucleation layer may be formed by physical vapor deposition (PVD), and the physical vapor deposition may be characterized by a deposition temperature of greater than or about 700° C. The methods may further include forming a patterned mask layer on the nucleation layer. The patterned mask layer may include openings that expose portions of the nucleation layer. Gallium-and-nitrogen-containing regions may be formed on the exposed portions of the nucleation layer. In additional embodiments, the nucleation layer may include a first and second portion separated by an interlayer that stop the propagation of at least some dislocations in the nucleation layer.