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公开(公告)号：US20230232727A1
公开(公告)日：2023-07-20
申请号：US18190971
申请日：2023-03-28
Applicant: Applied Materials, Inc.
Inventor： Deepak Kamalanathan , Archana Kumar , Siddarth Krishnan
CPC classification number: H10N70/245 , H10N70/021 , H10N70/8833
Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.
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公开(公告)号：US11790989B2
公开(公告)日：2023-10-17
申请号：US17329008
申请日：2021-05-24
Applicant: Applied Materials, Inc.
Inventor： Deepak Kamalanathan , Siddarth Krishnan , Archana Kumar , Fuxi Cai , Federico Nardi
CPC classification number: G11C13/0097 , G11C13/004 , G11C13/0038 , G11C13/0069
Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.
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公开(公告)号：US20230178375A1
公开(公告)日：2023-06-08
申请号：US17541582
申请日：2021-12-03
Applicant: Applied Materials, Inc.
Inventor： Kunal Bhatnagar , Wei Liu , Shashank Sharma , Archana Kumar , Mohith Verghese , Jose Alexandro Romero
IPC: H01L21/28 , H01L29/49 , H01L29/40 , H01L21/285 , H01L21/3215
CPC classification number: H01L21/28088 , H01L21/3215 , H01L21/28556 , H01L29/401 , H01L29/4966
Abstract: Method of forming film stacks and film stacks for electronic devices are described herein. The methods comprise depositing a molybdenum nucleation layer on a gate oxide layer; depositing a molybdenum layer on the molybdenum nucleation layer; and performing a plasma nitridation process to insert nitrogen atoms into the molybdenum layer to form a work function modulating layer having an effective work function ≤ 4.5 eV. The plasma nitridation process comprises exposing the molybdenum layer to a radical-rich plasma comprising one or more of N2 or NH3. Some methods further comprise one or more of annealing the work function modulating layer, depositing a conductive layer on the work function modulating layer, or performing an etch process.
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公开(公告)号：US11605741B2
公开(公告)日：2023-03-14
申请号：US17102148
申请日：2020-11-23
Applicant: Applied Materials, Inc.
Inventor： Joshua S. Holt , Lan Yu , Tyler Sherwood , Archana Kumar , Nicolas Louis Gabriel Breil , Siddarth Krishnan
IPC: H01L29/872 , H01L21/28 , H01L29/45 , H01L29/861 , H01L29/66 , H01L29/47
Abstract: Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.
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公开(公告)号：US20220165574A1
公开(公告)日：2022-05-26
申请号：US17102148
申请日：2020-11-23
Applicant: Applied Materials, Inc.
Inventor： Joshua S. Holt , Lan Yu , Tyler Sherwood , Archana Kumar , Nicolas Louis Gabriel Breil , Siddarth Krishnan
IPC: H01L21/28 , H01L29/66 , H01L29/861 , H01L29/45
Abstract: Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.
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Patent Agency Ranking
公开(公告)号：US20250029835A1
公开(公告)日：2025-01-23
申请号：US18770960
申请日：2024-07-12
Applicant: Applied Materials, Inc.
Inventor： Ryan Ley , Archana Kumar , Michel El Khoury Maroun , Benjamin D. Briggs
Abstract: Exemplary semiconductor processing methods may include performing a treatment operation on a substrate housed within a first processing region of a first semiconductor processing chamber. The methods may include providing a nitrogen-containing precursor to the first processing region. The methods may include forming plasma effluents of the nitrogen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the nitrogen-containing precursor. The contacting may nitride a surface of the substrate. The methods may include transferring the substrate from the first processing region of the first semiconductor processing chamber to a second processing region of a second semiconductor processing chamber. The methods may include providing one or more deposition precursors to the second processing region. The methods may include contacting the substrate with the one or more deposition precursors. The contacting may deposit a layer of dielectric material on the substrate.
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公开(公告)号：US12178146B2
公开(公告)日：2024-12-24
申请号：US18190971
申请日：2023-03-28
Applicant: Applied Materials, Inc.
Inventor： Deepak Kamalanathan , Archana Kumar , Siddarth Krishnan
Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.
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公开(公告)号：US20230361242A1
公开(公告)日：2023-11-09
申请号：US17736843
申请日：2022-05-04
Applicant: Applied Materials, Inc.
Inventor： Michel Khoury , Archana Kumar , Jeffrey W. Anthis , Ryan Ley , Alfredo Granados
IPC: H01L33/00 , H01L25/075
CPC classification number: H01L33/0095 , H01L25/0753 , H01L33/0075
Abstract: A mesa etch may form the geometry of microLED structures. However, the mesa etch may induce defects in the microLED structures that decreases the efficiency of the microLEDs. To correct these defects, a dry etch process may be performed that incrementally removes the surface layers of the microLED structures with the defects. The dry etch may be configured to incrementally remove a small outer layer, and thus may preserve the overall shape of the microLED structures while leaving a smooth surface for the application of a dielectric layer. The dry etch process may include two steps that are repeatedly performed. A first gas may react with the surface to form a gallium compound layer, and a second gas may then selectively remove that layer. The dry etch may include plasma-based etches or reactive thermal etches.
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公开(公告)号：US11616195B2
公开(公告)日：2023-03-28
申请号：US16883009
申请日：2020-05-26
Applicant: Applied Materials, Inc.
Inventor： Deepak Kamalanathan , Archana Kumar , Siddarth Krishnan
IPC: H01L45/00
Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.
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公开(公告)号：US20210280247A1
公开(公告)日：2021-09-09
申请号：US17329008
申请日：2021-05-24
Applicant: Applied Materials, Inc.
Inventor： Deepak Kamalanathan , Siddarth Krishnan , Archana Kumar , Fuxi Cai , Federico Nardi
IPC: G11C13/00
Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.
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