公开(公告)号：US20040063328A1

公开(公告)日：2004-04-01

申请号：US10263019

申请日：2002-10-01

Applicant: Applied Materials, Inc.

Inventor： Jianping Wen ,  Meihua Shen ,  Hung-Kwei Hu

IPC: H01L021/461

CPC classification number: H01L21/32137

Abstract: In a method of etching a substrate, a substrate is provided in a process zone, the substrate having a pattern of features comprising dielectric covering semiconductor. In a first stage, an energized first etching gas is provided in the process zone, the energized first etching gas having a first selectivity of etching dielectric to semiconductor of at least about 1.8:1, wherein the dielectric is etched preferentially to the semiconductor to etch through the dielectric to at least partially expose the semiconductor. In a second stage, an energized second etching gas is provided in the process zone, the energized second etching gas having a second selectivity of etching dielectric to semiconductor of less than about 1:1.8, wherein the semiconductor is etched preferentially to the dielectric.

Abstract translation: 在蚀刻衬底的方法中，在工艺区域中设置衬底，衬底具有包括电介质覆盖半导体的特征图案。 在第一阶段中，在处理区域中提供通电的第一蚀刻气体，所激发的第一蚀刻气体具有至少约1.8:1的对半导体的蚀刻电介质的第一选择性，其中电介质优先蚀刻到半导体以蚀刻 通过电介质至少部分地暴露半导体。 在第二阶段中，在处理区域中提供通电的第二蚀刻气体，所通电的第二蚀刻气体具有小于约1：1.8的蚀刻电介质至半导体的第二选择性，其中半导体优先蚀刻到电介质。

公开(公告)号：US20040084411A1

公开(公告)日：2004-05-06

申请号：US10286297

申请日：2002-10-31

Applicant: Applied Materials, Inc.

Inventor： Yan Du ,  Shashank Deshmukh ,  Meihua Shen ,  Steven Jones

IPC: H01L021/461

CPC classification number: H01L21/31116 ,  H01L21/32139

Abstract: Disclosed herein is a method of pattern etching a layer of a silicon-containing dielectric material. The method employs a plasma source gas comprising CH2F2, CF4, and O2, where a volumetric ratio of CH2F2 to CF4 is within the range of about 1:2 to about 3:1, and where O2 comprises about 2 to about 20 volume % of the plasma source gas. Etching is performed at a process chamber pressure within the range of about 4 mTorr to about 10 mTorr. The method provides a selectivity for etching a silicon-containing dielectric layer relative to photoresist of at least 2:1. The method also provides an etch profile sidewall angle ranging from about 84null to about 90null between the etched silicon-containing dielectric layer and an underlying horizontal layer in a semiconductor structure.

Abstract translation: 本文公开了一种图案蚀刻含硅介电材料层的方法。 该方法采用包含CH 2 F 2，CF 4和O 2的等离子体源气体，其中CH 2 F 2与CF 4的体积比在约1:2至约3:1的范围内，并且其中O 2包含约2至约20体积％ 等离子体源气体。 在约4mTorr至约10mTorr的范围内的处理室压力下进行蚀刻。 该方法提供了相对于光致抗蚀剂蚀刻含硅电介质层至少2:1的选择性。 该方法还提供在半导体结构中蚀刻的含硅介电层和下面的水平层之间的约84°至约90°的蚀刻轮廓侧壁角。

公开(公告)号：US20040018739A1

公开(公告)日：2004-01-29

申请号：US10206252

申请日：2002-07-26

Applicant: Applied Materials, Inc.

Inventor： Farid Abooameri ,  Shashank C. Deshmukh ,  Meihua Shen ,  Stephanie S. Cheng ,  Nicolas Gani ,  Thorsten B. Lill

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/32137

Abstract: One embodiment of the present invention is a method used to fabricate an integrated circuit device on a wafer or substrate at a stage where a gate oxide is disposed over the wafer or substrate, a polysilicon layer is disposed thereover, a patterned hardmask is disposed thereover, a patterned antireflective coating is disposed thereover, and a patterned photoresist is disposed thereover, the method including steps of: (a) before stripping the photoresist, etching the polysilicon utilizing a first etch chemistry for a first period of time; and (b) etching the polysilicon utilizing a second etch chemistry for a second period of time.

Abstract translation: 本发明的一个实施例是一种用于在晶片或衬底上制造集成电路器件的方法，其中栅极氧化物设置在晶片或衬底之上，多晶硅层设置在晶片或衬底之上，其上设置有图案化的硬掩模， 图案化的抗反射涂层设置在其上，并且其上布置有图案化的光致抗蚀剂，所述方法包括以下步骤：（a）在剥离光致抗蚀剂之前，使用第一蚀刻化学品在第一时间段内蚀刻多晶硅; 和（b）在第二时间段内利用第二蚀刻化学品蚀刻所述多晶硅。

公开(公告)号：US20030148622A1

公开(公告)日：2003-08-07

申请号：US10279320

申请日：2002-10-23

Applicant: Applied Materials, Inc.

Inventor： Meihua Shen ,  Yan Du ,  Nicolas Gani ,  Oranna Yauw ,  Hakeem M. Oluseyi

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/28088 ,  H01L21/32136 ,  H01L29/4966

Abstract: Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

Abstract translation: 提供了直接形成在栅极电介质上的蚀刻电极的方法。 在一个方面，提供了一种蚀刻工艺，其包括主蚀刻步骤，软着色步骤和过蚀刻步骤。 在另一方面，描述了一种方法，其包括执行具有良好蚀刻速率均匀性和良好轮廓均匀性的主蚀刻，执行软着色步骤，其中可以确定金属/金属屏障界面，以及执行过蚀刻步骤以选择性地去除 金属屏障，而不会对电介质产生负面影响。 在另一方面，提供了一种方法，其包括用于大量去除电极材料的第一非选择性蚀刻化学品，具有端点能力的第二中间选择性蚀刻化学品，然后选择蚀刻化学物质停止在栅极电介质上。

公开(公告)号：US20040018741A1

公开(公告)日：2004-01-29

申请号：US10206634

申请日：2002-07-26

Applicant: Applied Materials, Inc.

Inventor： Shashank C. Deshmukh ,  Steven J. Jones ,  Meihua Shen ,  Thorsten B. Lill ,  John P. Holland ,  Michael Barnes ,  Dragan V. Podlesnik

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/31116 ,  H01J37/321

Abstract: One embodiment of the present invention is an etching method for use in fabricating an integrated circuit device on a wafer or substrate in an inductively coupled plasma reactor in a passivation-driven etch chemistry, which method includes steps of: (a) providing a passivation-driven etch chemistry precursor in a chamber of the reactor wherein a first coil is disposed to supply energy primarily to an outer portion of the chamber and a second coil is disposed to supply energy primarily to an inner portion of the chamber; and (b) providing power to the first coil and the second coil in a ratio of power supplied to the first coil and power supplied to the second coil greater than 1.

Abstract translation: 本发明的一个实施例是一种用于在钝化驱动的蚀刻化学中在电感耦合等离子体反应器中的晶片或衬底上制造集成电路器件的蚀刻方法，该方法包括以下步骤：（a）提供钝化 - 反应器腔室中的驱动蚀刻化学前体，其中设置第一线圈以将能量主要供应到腔室的外部，并且第二线圈被设置为主要将能量供应到腔室的内部; 和（b）以提供给第一线圈的功率与供给到第二线圈的功率的比率大于1，向第一线圈和第二线圈供电。

公开(公告)号：US20030082919A1

公开(公告)日：2003-05-01

申请号：US10040109

申请日：2001-10-29

Applicant: Applied Materials, Inc.

Inventor： Wilfred Pau ,  Meihua Shen ,  Jeffrey D. Chinn

IPC: H01L021/302

CPC classification number: H01L22/26 ,  H01L21/32137

Abstract: We have discovered a method of detecting the approach of an endpoint during the etching of a material within a recess such as a trench or a contact via. The method provides a clear and distinct inflection endpoint signal, even for areas of a substrate containing isolated features. The method includes etching the material in the recess and using thin film interferometric endpoint detection to detect an endpoint of the etch process, where the interferometric incident light beam wavelength is tailored to the material being etched; the spot size of the substrate illuminated by the light beam is sufficient to provide adequate signal intensity from the material being etched; and the refractive index of the material being etched is sufficiently different from the refractive index of other materials contributing to reflected light from the substrate, that the combination of the light beam wavelength, the spot size, and the difference in refractive index provides a clear and distinct endpoint signal.

公开(公告)号：US20040152331A1

公开(公告)日：2004-08-05

申请号：US10660151

申请日：2003-09-11

Applicant: Applied Materials, Inc.

Inventor： Songlin Xu ,  Thorsten B. Lill ,  Yeajer Arthur Chen ,  Mohit Jain ,  Nicolas Gani ,  Shing-Li Sung ,  Jitske K. Kretz ,  Meihua Shen ,  Farid Abooameri

IPC: H01L021/3205 ,  H01L021/4763

CPC classification number: H01J37/321 ,  H01J37/32935 ,  H01L21/28035 ,  H01L21/32137

Abstract: The present invention provides a process of etching polysilicon gates using a silicon dioxide hard mask. The process includes exposing a substrate with a polysilicon layer formed thereon to a plasma of a process gas, which includes a base gas and an additive gas. The base gas includes HBr, Cl2, O2, and the additive gas is NF3 and/or N2. By changing a volumetric flow ratio of the additive gas to the base gas, the etch rate selectivity of polysilicon to silicon dioxide may be increased, which allows for a thinner hard mask, better protection of the gate oxide layer, and better endpoint definition and control. Additionally, when the polysilicon layer includes both N-doped and P-doped regions, the additive gas includes both NF3 and N2, and by changing a volumetric flow ratio of NF3 to N2, the etching process may be tailored to provide optimal results in N/P loading and microloading.

Abstract translation: 本发明提供使用二氧化硅硬掩模蚀刻多晶硅栅的方法。 该方法包括将其上形成有多晶硅层的衬底暴露于包括基础气体和添加气体的工艺气体的等离子体。 基础气体包括HBr，Cl2，O2，添加气体是NF3和/或N2。 通过改变添加气体与基础气体的体积流量比，可以增加多晶硅对二氧化硅的蚀刻速率选择性，这允许更薄的硬掩模，更好地保护栅极氧化物层，以及更好的端点定义和控制 。 另外，当多晶硅层包括N掺杂区域和P掺杂区域时，添加气体都包括NF3和N2，并且通过将NF 3的体积流量比改变为N2，可以调整蚀刻工艺以在N / P装载和微型加载。

公开(公告)号：US20040018742A1

公开(公告)日：2004-01-29

申请号：US10379980

申请日：2003-03-04

Applicant: Applied Materials, Inc.

Inventor： Jim Zhongyi He ,  Meihua Shen ,  Hong Du ,  Scott M. Williams

IPC: H01L021/302 ,  H01L021/461

CPC classification number: G03F7/405 ,  G03F7/094 ,  G03F7/427 ,  H01L21/0274 ,  H01L21/31138

Abstract: The present invention includes a method for patterning a bilayer resist having a patterned upper resist layer over a lower resist layer formed on a substrate. In one embodiment of the present invention, the method includes an optional upper resist layer trimming step, an upper resist layer treatment step, and a lower resist layer etching step. In the upper resist layer trimming step, the upper resist layer is trimmed in a plasma of a first process gas. In the upper resist layer treatment step, the upper resist layer is treated in a plasma of a second process gas to increase its etch resistance during the subsequent lower resist layer etching step. In the lower resist etching step, the lower resist layer is etched in a plasma of a third process gas, using the upper resist layer as a mask.

Abstract translation: 本发明包括在形成在基板上的下抗蚀剂层上形成图案化的上抗蚀剂层的双层抗蚀剂图案化方法。 在本发明的一个实施例中，该方法包括可选的上抗蚀剂层修整步骤，上抗蚀剂层处理步骤和下抗蚀剂层蚀刻步骤。 在上抗蚀剂层修整步骤中，在第一工艺气体的等离子体中修整上抗蚀剂层。 在上抗蚀剂层处理步骤中，在第二处理气体的等离子体中处理上抗蚀剂层，以在随后的较低抗蚀剂层蚀刻步骤期间增加其耐蚀刻性。 在较低抗蚀剂蚀刻步骤中，使用上抗蚀剂层作为掩模，在第三处理气体的等离子体中蚀刻下抗蚀剂层。