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公开(公告)号：US12094787B2
公开(公告)日：2024-09-17
申请号：US17393037
申请日：2021-08-03
Applicant: Applied Materials, Inc.
Inventor： Milan Pesic
Abstract: A method of characterizing defects in semiconductor layers may include forming a first electrode, a first barrier layer, a semiconductor layer, and a second electrode, where the first barrier layer is between the first electrode and the semiconductor layer, and the semiconductor layer is between the first barrier layer and the second electrode. The method may also include causing current to flow through the semiconductor layer, where the first barrier layer prevents the current from entering a conduction band of the semiconductor layer and instead causes current to flow through defects in the semiconductor layer. The method may also include characterizing the defects in the semiconductor layer based on the current flowing through the defects in the semiconductor layer.
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2.发明申请公开(公告)号：US20220059764A1
公开(公告)日：2022-02-24
申请号：US17510370
申请日：2021-10-25
Applicant: Applied Materials, Inc.
Inventor： Milan Pesic , Andrea Padovani , Bastien Beltrando
Abstract: A selector device for a memory cell in a memory array may include a first electrode, and a separator that include a first region of a single-composition layer of a mixed ionic-electronic conduction material with a first concentration of defects; and a second region of a single-composition layer of a transitional metal oxide with a second concentration of defects that is different from the first concentration of defects. The selector device may also include a second electrode, where the separator is between the first electrode and the second electrode.
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公开(公告)号：US12141688B2
公开(公告)日：2024-11-12
申请号：US17380318
申请日：2021-07-20
Applicant: Applied Materials, Inc.
Inventor： Milan Pesic , Shruba Gangopadhyay , Muthukumar Kaliappan , Michael Haverty
Abstract: A crested barrier memory device may include a first electrode, a first self-rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately −0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.
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公开(公告)号：US20240341082A1
公开(公告)日：2024-10-10
申请号：US18620296
申请日：2024-03-28
Applicant: Applied Materials, Inc.
Inventor： Zhijun Chen , Fredrick Fishburn , Milan Pesic
IPC: H10B12/00
CPC classification number: H10B12/315 , H10B12/05 , H10B12/482 , H10B12/485
Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) array access transistors with improved hole distribution. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include a p-doped bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, where the first channel is spaced apart from the second channel in a row extending in the second horizontal direction.
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公开(公告)号：US20220140146A1
公开(公告)日：2022-05-05
申请号：US17084953
申请日：2020-10-30
Applicant: Applied Materials, Inc.
Inventor： Milan Pesic
IPC: H01L29/78 , H01L21/28 , G11C11/22 , H01L27/11585
Abstract: An enhanced ferroelectric transistor may include Interface switching modulation (ISM) layers along with a ferroelectric layer in the gate of the transistor to increase a memory window while maintaining relatively low operating voltages. The enhanced ferroelectric transistor may be implemented as a memory device storing more than two bits of information in each memory cell. An enhanced ferroelectric tunnel junction device may include ISM layers and a ferroelectric layer to amplify the tunneling barriers in the device. The ISM layers may form material dipoles that add to the effect of ferroelectric dipoles in the ferroelectric material.
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Patent Agency Ranking
公开(公告)号：US20220263022A1
公开(公告)日：2022-08-18
申请号：US17734634
申请日：2022-05-02
Applicant: Applied Materials, Inc.
Inventor： Milan Pesic , Luca Larcher , Bastien Beltrando
Abstract: A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.
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公开(公告)号：US20220069214A1
公开(公告)日：2022-03-03
申请号：US17010155
申请日：2020-09-02
Applicant: Applied Materials, Inc.
Inventor： Milan Pesic , Bastien Beltrando
Abstract: A device may include a first electrode, a barrier layer, and a tunneling layer having a first dielectric constant. The barrier layer may be between the first electrode and the tunneling layer. The device may also include an active layer having a second dielectric constant. The tunneling layer may be between the first electrode and the active layer. The device may further include a second electrode. The active layer may be between the tunneling layer and the second electrode.
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公开(公告)号：US20210151674A1
公开(公告)日：2021-05-20
申请号：US16689987
申请日：2019-11-20
Applicant: Applied Materials, Inc.
Inventor： Milan Pesic , Luca Larcher , Bastien Beltrando
Abstract: A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.
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公开(公告)号：US20210034953A1
公开(公告)日：2021-02-04
申请号：US16530714
申请日：2019-08-02
Applicant: Applied Materials, Inc.
Inventor： Milan Pesic
IPC: G06N3/063 , H01L27/088
Abstract: A semiconductor device that implements artificial neurons and synapses together on the semiconductor device includes a plurality of fins formed on the semiconductor device, and a plurality of gates formed around the plurality of fins to form a plurality of fin field-effect transistors (FinFETs). The plurality of FinFETs may form one or more artificial synapses and one or more artificial neurons. Each of the one or more artificial synapses may include two or more of the plurality of gates. Each of the one or more artificial neurons comprises one of the plurality of gates.
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公开(公告)号：US20250006563A1
公开(公告)日：2025-01-02
申请号：US18882362
申请日：2024-09-11
Applicant: Applied Materials, Inc.
Inventor： Milan Pesic
Abstract: A method of characterizing defects in semiconductor layers may include forming a first electrode, a first barrier layer, a semiconductor layer, and a second electrode, where the first barrier layer is between the first electrode and the semiconductor layer, and the semiconductor layer is between the first barrier layer and the second electrode. The method may also include causing current to flow through the semiconductor layer, where the first barrier layer prevents the current from entering a conduction band of the semiconductor layer and instead causes current to flow through defects in the semiconductor layer. The method may also include characterizing the defects in the semiconductor layer based on the current flowing through the defects in the semiconductor layer.
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