公开(公告)号：US20230040358A1

公开(公告)日：2023-02-09

申请号：US17395854

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/40

Abstract: Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

公开(公告)号：US20220165863A1

公开(公告)日：2022-05-26

申请号：US17102573

申请日：2020-11-24

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  David J. Lee ,  Jason Appell

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/203

Abstract: Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.

公开(公告)号：US20240145217A1

公开(公告)日：2024-05-02

申请号：US17979545

申请日：2022-11-02

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Eric Jay Simmons, JR. ,  Jared Traynor ,  Wei Zou ,  Miguel Fung ,  Samphy Hong

IPC: H01J37/32

CPC classification number: H01J37/32412 ,  H01J2237/2001 ,  H01J2237/20214 ,  H01J2237/20221 ,  H01J2237/3365

Abstract: Methods for processing a dielectric film to improve its uniformity of thickness and refractive index are disclosed. The dielectric film is deposited using conventional approaches, such as chemical vapor deposition (CVD) or spin coating. The workpiece, with the applied dielectric film is then processed to improve the uniformity of the thickness. This processing may comprise implanting a thinning species to the thicker portions of the dielectric film to reduce the thickness of these portions. The thinning species may be silicon or another suitable species. This processing may alternatively or additionally include implanting a thickening species to the thinner portions of the dielectric film to increase their thickness. The thickening species may be helium or another suitable species. This approach may reduce the variation in thickness by 50% or more.

公开(公告)号：US20220415657A1

公开(公告)日：2022-12-29

申请号：US17362946

申请日：2021-06-29

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Judy Campbell Soukup

IPC: H01L21/265 ,  H01L21/266

Abstract: Disclosed herein are methods for forming a buried layer using a low-temperature ion implant. In some embodiments a method may include providing an opening through a mask, wherein the mask is formed directly atop a substrate, and forming a buried layer in the substrate by performing a low-temperature ion implant through the opening of the mask. The method may further include forming an oxide layer over the substrate including over the buried layer.

公开(公告)号：US11387338B1

公开(公告)日：2022-07-12

申请号：US17155662

申请日：2021-01-22

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Lei Zhong ,  David Jon Lee ,  Felix Levitov ,  Carlos Caballero ,  Durgaprasad Chaturvedula

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate.

公开(公告)号：US20240128131A1

公开(公告)日：2024-04-18

申请号：US17966634

申请日：2022-10-14

Applicant: Applied Materials, Inc.

Inventor： Avishay Vaxman ,  Qintao Zhang ,  Jeffrey P. Koch ,  David P. Surdock ,  Wayne R. Swart ,  David J. Lee ,  Samphy Hong ,  Aldrin Bernard Vincent Eddy ,  Daniel G. Deyo

IPC: H01L21/66 ,  G06T7/00 ,  G06T7/80 ,  H04N5/225 ,  H04N5/232

CPC classification number: H01L22/24 ,  G06T7/001 ,  G06T7/80 ,  H01L22/26 ,  H04N5/2256 ,  H04N5/23222 ,  H04N5/23229 ,  G06T2207/30148

Abstract: A camera may capture reflected light from the surface of the wafer during a semiconductor process that adds or removes material from the wafer, such as an etch process. To accurately determine an endpoint for the process, a camera sampling rate and light source intensity may be optimized in the process recipe. Optimizing the light source intensity may include characterizing light intensities that will be reflected from the waiver using an image of the wafer. Pixel intensities may be used to adjust the light source intensity to compensate for more complex wafer patterns. Optimizing the camera sampling rates may include nondestructively rotating a view of the wafer and converting the sampled intensities to the frequency domain. The camera sampling rate may be increased or decreased to remove spatial noise from the image without oversampling unnecessarily. These optimized parameters may then generate a clean, repeatable trace for endpoint determination.

公开(公告)号：US11695060B2

公开(公告)日：2023-07-04

申请号：US17127298

申请日：2020-12-18

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Lei Zhong ,  David J. Lee ,  Felix Levitov

IPC: H01L21/04 ,  H01L21/28 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66734 ,  H01L21/2822 ,  H01L29/42368

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.

公开(公告)号：US20220415656A1

公开(公告)日：2022-12-29

申请号：US17358244

申请日：2021-06-25

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Vittoriano Ruscio ,  Wei Zou ,  David J. Lee

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739

Abstract: Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

公开(公告)号：US20220359710A1

公开(公告)日：2022-11-10

申请号：US17307809

申请日：2021-05-04

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Hans-Joachim L. Gossmann

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04

Abstract: Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.

公开(公告)号：US20220199802A1

公开(公告)日：2022-06-23

申请号：US17130605

申请日：2020-12-22

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Wei Zou ,  Samphy Hong

IPC: H01L29/66 ,  H01L21/67

Abstract: A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.